Hi Cedric,
> Subject: Re: [PATCH v2 07/11] hw/i2c/aspeed: support high part dram offset for
> DMA 64 bits
>
> On 9/3/24 05:06, Jamin Lin wrote:
> > Hi Cedric,
> >
> >> Subject: Re: [PATCH v2 07/11] hw/i2c/aspeed: support high part dram
> >&
On 9/3/24 05:06, Jamin Lin wrote:
Hi Cedric,
Subject: Re: [PATCH v2 07/11] hw/i2c/aspeed: support high part dram offset for
DMA 64 bits
Jamin,
Please adjust commit title
What do you think if I change the commit title as following.
hw/i2c/aspeed: Add support for dma_dram_offset attribute
Hi Cedric,
> Subject: Re: [PATCH v2 07/11] hw/i2c/aspeed: support high part dram offset for
> DMA 64 bits
>
> Jamin,
>
> Please adjust commit title
What do you think if I change the commit title as following.
hw/i2c/aspeed: Add support for dma_dram_offset attribute bits
Jamin,
Please adjust commit title
On 8/8/24 04:49, Jamin Lin wrote:
ASPEED AST2700 SOC is a 64 bits quad core CPUs (Cortex-a35)
And the base address of dram is "0x4 " which
is 64bits address.
The AST2700 support the maximum DRAM size is 8 GB.
The DRAM physical address range is from "0x
ASPEED AST2700 SOC is a 64 bits quad core CPUs (Cortex-a35)
And the base address of dram is "0x4 " which
is 64bits address.
The AST2700 support the maximum DRAM size is 8 GB.
The DRAM physical address range is from "0x4__" to
"0x5__".
The DRAM offset range is from "0x0_000
