Re: [PATCH v2 08/15] hw/riscv/riscv-iommu: add Address Translation Cache (IOATC)

On 5/8/24 04:26, Frank Chang wrote: Hi Daniel, Daniel Henrique Barboza 於 2024年3月8日 週五 上午12:05寫道： From: Tomasz Jeznach The RISC-V IOMMU spec predicts that the IOMMU can use translation caches to hold entries from the DDT. This includes implementation for all cache commands that are marked

Re: [PATCH v2 08/15] hw/riscv/riscv-iommu: add Address Translation Cache (IOATC)

Hi Daniel, Daniel Henrique Barboza 於 2024年3月8日 週五 上午12:05寫道： > > From: Tomasz Jeznach > > The RISC-V IOMMU spec predicts that the IOMMU can use translation caches > to hold entries from the DDT. This includes implementation for all cache > commands that are marked as 'not implemented'. > > There

[PATCH v2 08/15] hw/riscv/riscv-iommu: add Address Translation Cache (IOATC)

From: Tomasz Jeznach The RISC-V IOMMU spec predicts that the IOMMU can use translation caches to hold entries from the DDT. This includes implementation for all cache commands that are marked as 'not implemented'. There are some artifacts included in the cache that predicts s-stage and g-stage e