Re: [PATCH v2 2/2] target/riscv/cpu_helper.c: Fix mxr bit behavior

On Tue, Nov 21, 2023 at 6:53 PM Ivan Klokov wrote: > > According to RISCV Specification sect 9.5 on two stage translation when > V=1 the vsstatus(mstatus in QEMU's terms) field MXR, which makes > execute-only pages readable, only overrides VS-stage page protection. > Setting MXR at HS-level(mstatu

Re: [PATCH v2 2/2] target/riscv/cpu_helper.c: Fix mxr bit behavior

On 11/21/23 04:17, Ivan Klokov wrote: According to RISCV Specification sect 9.5 on two stage translation when V=1 the vsstatus(mstatus in QEMU's terms) field MXR, which makes execute-only pages readable, only overrides VS-stage page protection. Setting MXR at HS-level(mstatus_hs), however, ove

[PATCH v2 2/2] target/riscv/cpu_helper.c: Fix mxr bit behavior

According to RISCV Specification sect 9.5 on two stage translation when V=1 the vsstatus(mstatus in QEMU's terms) field MXR, which makes execute-only pages readable, only overrides VS-stage page protection. Setting MXR at HS-level(mstatus_hs), however, overrides both VS-stage and G-stage execute-on