Re: [PATCH v2 2/6] target/riscv: Add Control Transfer Records CSR definitions.

Hi Rajnesh, On 2024/6/19 下午 11:27, Rajnesh Kanwal wrote: The Control Transfer Records (CTR) extension provides a method to record a limited branch history in register-accessible internal chip storage. This extension is similar to Arch LBR in x86 and BRBE in ARM. The Extension has been stable

Re: [PATCH v2 2/6] target/riscv: Add Control Transfer Records CSR definitions.

On Thu, Jun 20, 2024 at 1:28 AM Rajnesh Kanwal wrote: > > The Control Transfer Records (CTR) extension provides a method to > record a limited branch history in register-accessible internal chip > storage. > > This extension is similar to Arch LBR in x86 and BRBE in ARM. > The Extension has been

[PATCH v2 2/6] target/riscv: Add Control Transfer Records CSR definitions.

The Control Transfer Records (CTR) extension provides a method to record a limited branch history in register-accessible internal chip storage. This extension is similar to Arch LBR in x86 and BRBE in ARM. The Extension has been stable and the latest release can be found here