GPRs and PC are 32-bit wide in loongarch32 mode.
Signed-off-by: Jiajie Chen <c...@jia.je>
---
configs/targets/loongarch64-softmmu.mak | 2 +-
gdb-xml/loongarch-base32.xml | 45 +++++++++++++++++++++++++
target/loongarch/cpu.c | 10 +++++-
target/loongarch/gdbstub.c | 32 ++++++++++++++----
4 files changed, 80 insertions(+), 9 deletions(-)
create mode 100644 gdb-xml/loongarch-base32.xml
diff --git a/configs/targets/loongarch64-softmmu.mak
b/configs/targets/loongarch64-softmmu.mak
index 9abc99056f..f23780fdd8 100644
--- a/configs/targets/loongarch64-softmmu.mak
+++ b/configs/targets/loongarch64-softmmu.mak
@@ -1,5 +1,5 @@
TARGET_ARCH=loongarch64
TARGET_BASE_ARCH=loongarch
TARGET_SUPPORTS_MTTCG=y
-TARGET_XML_FILES= gdb-xml/loongarch-base64.xml gdb-xml/loongarch-fpu.xml
+TARGET_XML_FILES= gdb-xml/loongarch-base32.xml gdb-xml/loongarch-base64.xml
gdb-xml/loongarch-fpu.xml
TARGET_NEED_FDT=y
diff --git a/gdb-xml/loongarch-base32.xml b/gdb-xml/loongarch-base32.xml
new file mode 100644
index 0000000000..af47bbd3da
--- /dev/null
+++ b/gdb-xml/loongarch-base32.xml
@@ -0,0 +1,45 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2022 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.loongarch.base">
+ <reg name="r0" bitsize="32" type="uint32" group="general"/>
+ <reg name="r1" bitsize="32" type="code_ptr" group="general"/>
+ <reg name="r2" bitsize="32" type="data_ptr" group="general"/>
+ <reg name="r3" bitsize="32" type="data_ptr" group="general"/>
+ <reg name="r4" bitsize="32" type="uint32" group="general"/>
+ <reg name="r5" bitsize="32" type="uint32" group="general"/>
+ <reg name="r6" bitsize="32" type="uint32" group="general"/>
+ <reg name="r7" bitsize="32" type="uint32" group="general"/>
+ <reg name="r8" bitsize="32" type="uint32" group="general"/>
+ <reg name="r9" bitsize="32" type="uint32" group="general"/>
+ <reg name="r10" bitsize="32" type="uint32" group="general"/>
+ <reg name="r11" bitsize="32" type="uint32" group="general"/>
+ <reg name="r12" bitsize="32" type="uint32" group="general"/>
+ <reg name="r13" bitsize="32" type="uint32" group="general"/>
+ <reg name="r14" bitsize="32" type="uint32" group="general"/>
+ <reg name="r15" bitsize="32" type="uint32" group="general"/>
+ <reg name="r16" bitsize="32" type="uint32" group="general"/>
+ <reg name="r17" bitsize="32" type="uint32" group="general"/>
+ <reg name="r18" bitsize="32" type="uint32" group="general"/>
+ <reg name="r19" bitsize="32" type="uint32" group="general"/>
+ <reg name="r20" bitsize="32" type="uint32" group="general"/>
+ <reg name="r21" bitsize="32" type="uint32" group="general"/>
+ <reg name="r22" bitsize="32" type="data_ptr" group="general"/>
+ <reg name="r23" bitsize="32" type="uint32" group="general"/>
+ <reg name="r24" bitsize="32" type="uint32" group="general"/>
+ <reg name="r25" bitsize="32" type="uint32" group="general"/>
+ <reg name="r26" bitsize="32" type="uint32" group="general"/>
+ <reg name="r27" bitsize="32" type="uint32" group="general"/>
+ <reg name="r28" bitsize="32" type="uint32" group="general"/>
+ <reg name="r29" bitsize="32" type="uint32" group="general"/>
+ <reg name="r30" bitsize="32" type="uint32" group="general"/>
+ <reg name="r31" bitsize="32" type="uint32" group="general"/>
+ <reg name="orig_a0" bitsize="32" type="uint32" group="general"/>
+ <reg name="pc" bitsize="32" type="code_ptr" group="general"/>
+ <reg name="badv" bitsize="32" type="code_ptr" group="general"/>
+</feature>
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index d31efe86da..ee6d45f1b0 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -710,7 +710,13 @@ static const struct SysemuCPUOps loongarch_sysemu_ops = {
static gchar *loongarch_gdb_arch_name(CPUState *cs)
{
- return g_strdup("loongarch64");
+ LoongArchCPU *cpu = LOONGARCH_CPU(cs);
+ CPULoongArchState *env = &cpu->env;
+ if (env->mode == LA64) {
+ return g_strdup("loongarch64");
+ } else {
+ return g_strdup("loongarch32");
+ }
}
static void loongarch_cpu_class_init(ObjectClass *c, void *data)
@@ -750,6 +756,8 @@ static void loongarch_cpu_class_init(ObjectClass *c, void
*data)
static void loongarch32_cpu_class_init(ObjectClass *c, void *data)
{
+ CPUClass *cc = CPU_CLASS(c);
+ cc->gdb_core_xml_file = "loongarch-base32.xml";
}
#define DEFINE_LOONGARCH_CPU_TYPE(model, initfn) \
diff --git a/target/loongarch/gdbstub.c b/target/loongarch/gdbstub.c
index 0752fff924..7c82204e92 100644
--- a/target/loongarch/gdbstub.c
+++ b/target/loongarch/gdbstub.c
@@ -34,16 +34,25 @@ int loongarch_cpu_gdb_read_register(CPUState *cs,
GByteArray *mem_buf, int n)
{
LoongArchCPU *cpu = LOONGARCH_CPU(cs);
CPULoongArchState *env = &cpu->env;
+ uint64_t val;
if (0 <= n && n < 32) {
- return gdb_get_regl(mem_buf, env->gpr[n]);
+ val = env->gpr[n];
} else if (n == 32) {
/* orig_a0 */
- return gdb_get_regl(mem_buf, 0);
+ val = 0;
} else if (n == 33) {
- return gdb_get_regl(mem_buf, env->pc);
+ val = env->pc;
} else if (n == 34) {
- return gdb_get_regl(mem_buf, env->CSR_BADV);
+ val = env->CSR_BADV;
+ }
+
+ if (0 <= n && n <= 34) {
+ if (env->mode == LA64) {
+ return gdb_get_reg64(mem_buf, val);
+ } else {
+ return gdb_get_reg32(mem_buf, val);
+ }
}
return 0;
}
@@ -52,15 +61,24 @@ int loongarch_cpu_gdb_write_register(CPUState *cs, uint8_t
*mem_buf, int n)
{
LoongArchCPU *cpu = LOONGARCH_CPU(cs);
CPULoongArchState *env = &cpu->env;
- target_ulong tmp = ldtul_p(mem_buf);
+ target_ulong tmp;
+ int read_length;
int length = 0;
+ if (env->mode == LA64) {
+ tmp = ldq_p(mem_buf);
+ read_length = 8;
+ } else {
+ tmp = ldl_p(mem_buf);
+ read_length = 4;
+ }
+
if (0 <= n && n < 32) {
env->gpr[n] = tmp;
- length = sizeof(target_ulong);
+ length = read_length;
} else if (n == 33) {
env->pc = tmp;
- length = sizeof(target_ulong);
+ length = read_length;
}
return length;
}
--
2.39.2
