在 2022/1/2 上午3:48, Richard Henderson 写道:
ol is the operation length; xl is the register length.
In this case, the operation length doesn't matter -- we're interested
in distinguishing RV32 and RV64, because that's where the change in
semantics comes from.
So both read and write fpr should
On 12/31/21 10:05 PM, Weiwei Li wrote:
在 2022/1/1 上午4:06, Richard Henderson 写道:
On 12/30/21 7:23 PM, Weiwei Li wrote:
+ if (reg_num != 0) {
+ switch (get_ol(ctx)) {
Oh, you should be using get_xl here and elsewhere in this patch, not get_ol.
Sorry. I don't know the difference betw
在 2022/1/1 上午4:06, Richard Henderson 写道:
On 12/30/21 7:23 PM, Weiwei Li wrote:
+ if (reg_num != 0) {
+ switch (get_ol(ctx)) {
Oh, you should be using get_xl here and elsewhere in this patch, not
get_ol.
Sorry. I don't know the difference between get_xl and get_ol. From gpr
regis
On 12/30/21 7:23 PM, Weiwei Li wrote:
+if (reg_num != 0) {
+switch (get_ol(ctx)) {
Oh, you should be using get_xl here and elsewhere in this patch, not get_ol.
r~
On 12/30/21 7:23 PM, Weiwei Li wrote:
From: liweiwei
- update extension check REQUIRE_ZFINX_OR_F
- update single float point register read/write
- disable nanbox_s check
Co-authored-by: ardxwe
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/fpu_helper.c
From: liweiwei
- update extension check REQUIRE_ZFINX_OR_F
- update single float point register read/write
- disable nanbox_s check
Co-authored-by: ardxwe
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/fpu_helper.c | 89 +++
target/riscv/helpe
