Re: [PATCH v2 6/8] accel/tcg: Uncache the host address for instruction fetch when tlb size < 1

On 4/18/23 16:06, Weiwei Li wrote: When PMP entry overlap part of the page, we'll set the tlb_size to 1, which will make the address in tlb entry set with TLB_INVALID_MASK, and the next access will again go through tlb_fill.However, this way will not work in tb_gen_code() => get_page_addr_code_ho

Re: [PATCH v2 6/8] accel/tcg: Uncache the host address for instruction fetch when tlb size < 1

On 2023/4/18 22:06, Weiwei Li wrote: When PMP entry overlap part of the page, we'll set the tlb_size to 1, which will make the address in tlb entry set with TLB_INVALID_MASK, and the next access will again go through tlb_fill.However, this way will not work in tb_gen_code() => get_page_addr_cod

[PATCH v2 6/8] accel/tcg: Uncache the host address for instruction fetch when tlb size < 1

When PMP entry overlap part of the page, we'll set the tlb_size to 1, which will make the address in tlb entry set with TLB_INVALID_MASK, and the next access will again go through tlb_fill.However, this way will not work in tb_gen_code() => get_page_addr_code_hostp(): the TLB host address will be c