Re: [PATCH v3 03/37] target/riscv: 16-bit Addition & Subtraction Instructions

2021-06-30 Thread Alistair Francis
On Thu, Jun 24, 2021 at 9:08 PM LIU Zhiwei wrote: > > Include 5 groups: Wrap-around (dropping overflow), Signed Halving, > Unsigned Halving, Signed Saturation, and Unsigned Saturation. > > Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Alistair > --- > target/riscv/helper.h

[PATCH v3 03/37] target/riscv: 16-bit Addition & Subtraction Instructions

2021-06-24 Thread LIU Zhiwei
Include 5 groups: Wrap-around (dropping overflow), Signed Halving, Unsigned Halving, Signed Saturation, and Unsigned Saturation. Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 30 ++ target/riscv/insn32.decode | 32 +++ target/riscv/insn_trans/trans_rvp.c.