Hi Xiaoyao,
On Fri, Aug 04, 2023 at 05:56:47PM +0800, Xiaoyao Li wrote:
> Date: Fri, 4 Aug 2023 17:56:47 +0800
> From: Xiaoyao Li
> Subject: Re: [PATCH v3 04/17] i386/cpu: Fix i/d-cache topology to core
> level for Intel CPU
>
> On 8/1/2023 6:35 PM, Zhao Liu wrote:
On 8/1/2023 6:35 PM, Zhao Liu wrote:
From: Zhao Liu
For i-cache and d-cache, the maximum IDs for CPUs sharing cache (
CPUID.04H.00H:EAX[bits 25:14] and CPUID.04H.01H:EAX[bits 25:14]) are
both 0,
This sounds like you are describing some architectural rules, which
misleads me. I suggest chang
From: Zhao Liu
For i-cache and d-cache, the maximum IDs for CPUs sharing cache (
CPUID.04H.00H:EAX[bits 25:14] and CPUID.04H.01H:EAX[bits 25:14]) are
both 0, and this means i-cache and d-cache are shared in the SMT level.
This is correct if there's single thread per core, but is wrong for the
hyp
