Hi Jiaxun,
On 1/18/21 2:17 AM, Jiaxun Yang wrote:
> Loongson IPI controller is a MMIO based simple level triggered
> interrupt controller. It will trigger IRQ to it's upstream
> processor when set register is written.
>
> It also has 4 64bit mailboxes to pass boot information to
> secondary proce
Hi, Jiaxun,
On Mon, Jan 18, 2021 at 9:17 AM Jiaxun Yang wrote:
>
> Loongson IPI controller is a MMIO based simple level triggered
> interrupt controller. It will trigger IRQ to it's upstream
> processor when set register is written.
>
> It also has 4 64bit mailboxes to pass boot information to
>
Loongson IPI controller is a MMIO based simple level triggered
interrupt controller. It will trigger IRQ to it's upstream
processor when set register is written.
It also has 4 64bit mailboxes to pass boot information to
secondary processor.
Signed-off-by: Jiaxun Yang
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include/hw/intc/loongso
