All performance monitor counters can trigger a counter negative condition if the proper MMCR0 bits are set. This patch does that for all PMCs that can count cycles by doing the following:
- pmc_counter_negative_enabled() will check whether a given PMC is eligible to trigger the counter negative alert; - get_counter_neg_timeout() will return the timeout for the counter negative condition for a given PMC, or -1 if the PMC is not able to trigger this alert; - the existing counter_negative_cond_enabled() now must consider the counter negative bit for PMCs 2-6, MMCR0_PMCjCE; - start_cycle_count_session() will start overflow timers for all eligible PMCs. Signed-off-by: Daniel Henrique Barboza <danielhb...@gmail.com> --- target/ppc/cpu.h | 1 + target/ppc/power8_pmu.c | 116 ++++++++++++++++++++++++++++++++++------ 2 files changed, 100 insertions(+), 17 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index ba93b30ae2..02177e584e 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -355,6 +355,7 @@ typedef struct ppc_v3_pate_t { #define MMCR0_FC14 PPC_BIT(58) /* MMCR0 Freeze Counters 1-4 bit */ #define MMCR0_FC56 PPC_BIT(59) /* MMCR0 Freeze Counters 5-6 bit */ #define MMCR0_PMC1CE PPC_BIT(48) /* MMCR0 PMC1 Condition Enabled */ +#define MMCR0_PMCjCE PPC_BIT(49) /* MMCR0 PMCj Condition Enabled */ #define MMCR1_EVT_SIZE 8 /* extract64() does a right shift before extracting */ diff --git a/target/ppc/power8_pmu.c b/target/ppc/power8_pmu.c index b2224d363a..9125ba29ae 100644 --- a/target/ppc/power8_pmu.c +++ b/target/ppc/power8_pmu.c @@ -131,9 +131,81 @@ static int64_t get_CYC_timeout(CPUPPCState *env, int sprn) return remaining_cyc; } +static bool pmc_counter_negative_enabled(CPUPPCState *env, int sprn) +{ + if (!pmc_is_running(env, sprn)) { + return false; + } + + switch (sprn) { + case SPR_POWER_PMC1: + return env->spr[SPR_POWER_MMCR0] & MMCR0_PMC1CE; + + case SPR_POWER_PMC2: + case SPR_POWER_PMC3: + case SPR_POWER_PMC4: + case SPR_POWER_PMC5: + case SPR_POWER_PMC6: + return env->spr[SPR_POWER_MMCR0] & MMCR0_PMCjCE; + + default: + break; + } + + return false; +} + +static int64_t get_counter_neg_timeout(CPUPPCState *env, int sprn) +{ + int64_t timeout = -1; + + if (!pmc_counter_negative_enabled(env, sprn)) { + return -1; + } + + if (env->spr[sprn] >= COUNTER_NEGATIVE_VAL) { + return 0; + } + + switch (sprn) { + case SPR_POWER_PMC1: + case SPR_POWER_PMC2: + case SPR_POWER_PMC3: + case SPR_POWER_PMC4: + switch (get_PMC_event(env, sprn)) { + case 0xF0: + if (sprn == SPR_POWER_PMC1) { + timeout = get_CYC_timeout(env, sprn); + } + break; + case 0x1E: + timeout = get_CYC_timeout(env, sprn); + break; + } + + break; + case SPR_POWER_PMC6: + timeout = get_CYC_timeout(env, sprn); + break; + default: + break; + } + + return timeout; +} + static bool counter_negative_cond_enabled(uint64_t mmcr0) { - return mmcr0 & MMCR0_PMC1CE; + return mmcr0 & (MMCR0_PMC1CE | MMCR0_PMCjCE); +} + +static void pmu_delete_timers(CPUPPCState *env) +{ + int i; + + for (i = 0; i < PMU_TIMERS_LEN; i++) { + timer_del(env->pmu_intr_timers[i]); + } } /* @@ -144,7 +216,8 @@ static bool counter_negative_cond_enabled(uint64_t mmcr0) static void start_cycle_count_session(CPUPPCState *env) { uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); - uint64_t timeout; + int64_t timeout; + int i; env->pmu_base_time = now; @@ -152,30 +225,32 @@ static void start_cycle_count_session(CPUPPCState *env) * Always delete existing overflow timers when starting a * new cycle counting session. */ - timer_del(env->pmu_intr_timers[0]); + pmu_delete_timers(env); if (!counter_negative_cond_enabled(env->spr[SPR_POWER_MMCR0])) { return; } - if (!pmc_is_running(env, SPR_POWER_PMC1)) { - return; - } + /* + * Scroll through all programmable PMCs start counter overflow + * timers for PM_CYC events, if needed. + */ + for (i = SPR_POWER_PMC1; i < SPR_POWER_PMC5; i++) { + timeout = get_counter_neg_timeout(env, i); - if (!(env->spr[SPR_POWER_MMCR0] & MMCR0_PMC1CE)) { - return; - } + if (timeout == -1) { + continue; + } - switch (get_PMC_event(env, SPR_POWER_PMC1)) { - case 0xF0: - case 0x1E: - timeout = get_CYC_timeout(env, SPR_POWER_PMC1); - break; - default: - return; + timer_mod(env->pmu_intr_timers[i - SPR_POWER_PMC1], + now + timeout); } - timer_mod(env->pmu_intr_timers[0], now + timeout); + /* Check for counter neg timeout in PMC6 */ + timeout = get_counter_neg_timeout(env, SPR_POWER_PMC6); + if (timeout != -1) { + timer_mod(env->pmu_intr_timers[PMU_TIMERS_LEN - 1], now + timeout); + } } static void cpu_ppc_pmu_timer_cb(void *opaque) @@ -193,6 +268,13 @@ static void cpu_ppc_pmu_timer_cb(void *opaque) /* Changing MMCR0_FC demands a new hflags compute */ hreg_compute_hflags(env); + + /* + * Delete all pending timers if we need to freeze + * the PMC. We'll restart them when the PMC starts + * running again. + */ + pmu_delete_timers(env); } update_cycles_PMCs(env); -- 2.31.1