>-Original Message-
>From: Jason Wang
>Subject: Re: [PATCH v3 14/17] intel_iommu: Set default aw_bits to 48 in
>scalable modern mode
>
>On Fri, Sep 27, 2024 at 2:39 PM Duan, Zhenzhong
> wrote:
>>
>>
>>
>> >-Original Message-----
>&g
On Fri, Sep 27, 2024 at 2:39 PM Duan, Zhenzhong
wrote:
>
>
>
> >-Original Message-
> >From: Jason Wang
> >Subject: Re: [PATCH v3 14/17] intel_iommu: Set default aw_bits to 48 in
> >scalable modern mode
> >
> >On Wed, Sep 11, 2024 at 1:27 PM
>-Original Message-
>From: Jason Wang
>Subject: Re: [PATCH v3 14/17] intel_iommu: Set default aw_bits to 48 in
>scalable modern mode
>
>On Wed, Sep 11, 2024 at 1:27 PM Zhenzhong Duan
> wrote:
>>
>> According to VTD spec, stage-1 page table could supp
On Wed, Sep 11, 2024 at 1:27 PM Zhenzhong Duan wrote:
>
> According to VTD spec, stage-1 page table could support 4-level and
> 5-level paging.
>
> However, 5-level paging translation emulation is unsupported yet.
> That means the only supported value for aw_bits is 48.
>
> So default aw_bits to 4
According to VTD spec, stage-1 page table could support 4-level and
5-level paging.
However, 5-level paging translation emulation is unsupported yet.
That means the only supported value for aw_bits is 48.
So default aw_bits to 48 in scalable modern mode. In other cases,
it is still default to 39
