On Tue, 2024-05-21 at 08:18 +0200, Cédric Le Goater wrote:
> On 5/21/24 08:11, Chalapathi V wrote:
> > On 18-05-2024 01:24, Miles Glenn wrote:
> > > Chalapathi,
> > >
> > > I'm having trouble seeing the benefit of breaking this commit out
> > > from
> > > patch 1/5. It seems like the two should b
On 5/21/24 08:11, Chalapathi V wrote:
On 18-05-2024 01:24, Miles Glenn wrote:
Chalapathi,
I'm having trouble seeing the benefit of breaking this commit out from
patch 1/5. It seems like the two should be merged into a single commit
responsible for adding the PNV SPI Controller model.
-Glenn
On 18-05-2024 01:24, Miles Glenn wrote:
Chalapathi,
I'm having trouble seeing the benefit of breaking this commit out from
patch 1/5. It seems like the two should be merged into a single commit
responsible for adding the PNV SPI Controller model.
-Glenn
I thought combining this with patch 1/
Chalapathi,
I'm having trouble seeing the benefit of breaking this commit out from
patch 1/5. It seems like the two should be merged into a single commit
responsible for adding the PNV SPI Controller model.
-Glenn
On Thu, 2024-05-16 at 11:33 -0500, Chalapathi V wrote:
> In this commit SPI shif
In this commit SPI shift engine and sequencer logic is implemented.
Shift engine performs serialization and de-serialization according to the
control by the sequencer and according to the setup defined in the
configuration registers. Sequencer implements the main control logic and
FSM to handle dat
