Re: [PATCH v3 3/3] hw/{misc, riscv}: pfsoc: add system controller as unimplemented

2022-12-05 Thread Alistair Francis
On Fri, Nov 18, 2022 at 8:57 AM Conor Dooley wrote: > > From: Conor Dooley > > The system controller on PolarFire SoC is access via a mailbox. The > control registers for this mailbox lie in the "IOSCB" region & the > interrupt is cleared via write to the "SYSREG" region. It also has a > QSPI con

[PATCH v3 3/3] hw/{misc, riscv}: pfsoc: add system controller as unimplemented

2022-11-17 Thread Conor Dooley
From: Conor Dooley The system controller on PolarFire SoC is access via a mailbox. The control registers for this mailbox lie in the "IOSCB" region & the interrupt is cleared via write to the "SYSREG" region. It also has a QSPI controller, usually connected to a flash chip, that is used for stori