Re: [PATCH v3 3/3] target/riscv: add support for svpbmt extension

在 2022/1/14 下午9:59, Anup Patel 写道: On Fri, Jan 14, 2022 at 7:11 AM Weiwei Li wrote: It uses two PTE bits, but otherwise has no effect on QEMU, since QEMU is sequentially consistent and doesn't model PMAs currently Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Tested-by: Heiko Stue

Re: [PATCH v3 3/3] target/riscv: add support for svpbmt extension

On Fri, Jan 14, 2022 at 7:11 AM Weiwei Li wrote: > > It uses two PTE bits, but otherwise has no effect on QEMU, since QEMU is > sequentially consistent and doesn't model PMAs currently > > Signed-off-by: Weiwei Li > Signed-off-by: Junqiang Wang > Tested-by: Heiko Stuebner > --- > target/riscv

[PATCH v3 3/3] target/riscv: add support for svpbmt extension

It uses two PTE bits, but otherwise has no effect on QEMU, since QEMU is sequentially consistent and doesn't model PMAs currently Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Tested-by: Heiko Stuebner --- target/riscv/cpu.c| 1 + target/riscv/cpu.h| 1 + target/riscv/