RE: [PATCH v3 5/6] hw/gpio/aspeed: Add AST2700 support

2024-09-26 Thread Jamin Lin
Hi Andrew, > > On Thu, 2024-09-26 at 15:45 +0800, Jamin Lin wrote: > > AST2700 integrates two set of Parallel GPIO Controller with maximum > > 212 control pins, which are 27 groups. > > (H, exclude pin: H7 H6 H5 H4) > > > > In the previous design of ASPEED SOCs, one register is used for > > setti

Re: [PATCH v3 5/6] hw/gpio/aspeed: Add AST2700 support

2024-09-26 Thread Andrew Jeffery
On Thu, 2024-09-26 at 15:45 +0800, Jamin Lin wrote: > AST2700 integrates two set of Parallel GPIO Controller > with maximum 212 control pins, which are 27 groups. > (H, exclude pin: H7 H6 H5 H4) > > In the previous design of ASPEED SOCs, > one register is used for setting one function for one set

[PATCH v3 5/6] hw/gpio/aspeed: Add AST2700 support

2024-09-26 Thread Jamin Lin via
AST2700 integrates two set of Parallel GPIO Controller with maximum 212 control pins, which are 27 groups. (H, exclude pin: H7 H6 H5 H4) In the previous design of ASPEED SOCs, one register is used for setting one function for one set which are 32 pins and 4 groups. ex: GPIO000 is used for setting