ednesday, September 18, 2024 10:27:16 PM
*To:* LIU Zhiwei ; qemu-devel@nongnu.org
*Cc:* qemu-ri...@nongnu.org ; pal...@dabbelt.com ;
alistair.fran...@wdc.com ; dbarb...@ventanamicro.com ;
liwei1...@gmail.com ; bmeng...@gmail.com ; Swung0x48
; TANG Tiancheng
*Subject:* Re: [PATCH v4 02/12] tcg/riscv:
c.com>
<mailto:alistair.fran...@wdc.com>;
dbarb...@ventanamicro.com<mailto:dbarb...@ventanamicro.com>
<mailto:dbarb...@ventanamicro.com>;
liwei1...@gmail.com<mailto:liwei1...@gmail.com>
<mailto:liwei1...@gmail.com>;
bmeng...@gmail.com<mailto:bmeng...@gmail.com
; qemu-devel@nongnu.org
*Cc:* qemu-ri...@nongnu.org ;
pal...@dabbelt.com ; alistair.fran...@wdc.com
; dbarb...@ventanamicro.com
; liwei1...@gmail.com
; bmeng...@gmail.com ;
Swung0x48 ; TANG Tiancheng
*Subject:* Re: [PATCH v4 02/12] tcg/riscv: Add basic support for vector
On 9/18/24 12:43,
Daniel Henrique Barboza writes:
> Hi Zhiwei,
>
> As Rixchard already pointed out, we must have a "Signed-off-by" tag with the
> "author" of
> the patch, and it must be the exact spelling. So in this case:
>
> Signed-off-by: Swung0x48
I'm afraid we need a legal name here, not a nickname.
> Mor
Hi Zhiwei,
On 9/11/24 10:26 AM, LIU Zhiwei wrote:
From: Swung0x48
The RISC-V vector instruction set utilizes the LMUL field to group
multiple registers, enabling variable-length vector registers. This
implementation uses only the first register number of each group while
reserving the other re
chard Henderson
Sent: Wednesday, September 18, 2024 10:27:16 PM
To: LIU Zhiwei ; qemu-devel@nongnu.org
Cc: qemu-ri...@nongnu.org ; pal...@dabbelt.com
; alistair.fran...@wdc.com ;
dbarb...@ventanamicro.com ; liwei1...@gmail.com
; bmeng...@gmail.com ; Swung0x48
; TANG Tiancheng
Subject: Re:
ngnu.org ;
pal...@dabbelt.com ; alistair.fran...@wdc.com
; dbarb...@ventanamicro.com
; liwei1...@gmail.com
; bmeng...@gmail.com ;
Swung0x48 ; TANG Tiancheng
*Subject:* Re: [PATCH v4 02/12] tcg/riscv: Add basic support for vector
On 9/18/24 12:43, LIU Zhiwei wrote:
>
> On 2024/9/18 18:
On 9/18/24 12:43, LIU Zhiwei wrote:
On 2024/9/18 18:11, Richard Henderson wrote:
On 9/18/24 07:17, LIU Zhiwei wrote:
On 2024/9/12 2:41, Richard Henderson wrote:
On 9/11/24 06:26, LIU Zhiwei wrote:
From: Swung0x48
The RISC-V vector instruction set utilizes the LMUL field to group
multiple r
On 2024/9/18 18:11, Richard Henderson wrote:
On 9/18/24 07:17, LIU Zhiwei wrote:
On 2024/9/12 2:41, Richard Henderson wrote:
On 9/11/24 06:26, LIU Zhiwei wrote:
From: Swung0x48
The RISC-V vector instruction set utilizes the LMUL field to group
multiple registers, enabling variable-length v
On 9/18/24 07:17, LIU Zhiwei wrote:
On 2024/9/12 2:41, Richard Henderson wrote:
On 9/11/24 06:26, LIU Zhiwei wrote:
From: Swung0x48
The RISC-V vector instruction set utilizes the LMUL field to group
multiple registers, enabling variable-length vector registers. This
implementation uses only t
On 2024/9/12 2:41, Richard Henderson wrote:
On 9/11/24 06:26, LIU Zhiwei wrote:
From: Swung0x48
The RISC-V vector instruction set utilizes the LMUL field to group
multiple registers, enabling variable-length vector registers. This
implementation uses only the first register number of each gro
On 9/11/24 06:26, LIU Zhiwei wrote:
From: Swung0x48
The RISC-V vector instruction set utilizes the LMUL field to group
multiple registers, enabling variable-length vector registers. This
implementation uses only the first register number of each group while
reserving the other register numbers w
From: Swung0x48
The RISC-V vector instruction set utilizes the LMUL field to group
multiple registers, enabling variable-length vector registers. This
implementation uses only the first register number of each group while
reserving the other register numbers within the group.
In TCG, each VEC_IR
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