Re: [SPAM] Re: [PATCH v4 08/16] aspeed/smc: support 64 bits dma dram address

On 5/27/24 18:06, Philippe Mathieu-Daudé wrote: Hi Jamin, On 27/5/24 10:02, Jamin Lin wrote: AST2700 support the maximum dram size is 8GiB and has a "DMA DRAM Side Address High Part(0x7C)" register to support 64 bits dma dram address. Add helper routines functions to compute the dma dram addres

Re: [PATCH v4 08/16] aspeed/smc: support 64 bits dma dram address

On 5/28/24 03:34, Jamin Lin wrote: Hi Cedric, On 5/27/24 10:02, Jamin Lin wrote: AST2700 support the maximum dram size is 8GiB and has a "DMA DRAM Side Address High Part(0x7C)" register to support 64 bits dma dram address. Add helper routines functions to compute the dma dram address, new fe

RE: [PATCH v4 08/16] aspeed/smc: support 64 bits dma dram address

Hi Philippe, > Hi Jamin, > > On 27/5/24 10:02, Jamin Lin wrote: > > AST2700 support the maximum dram size is 8GiB and has a "DMA DRAM > Side > > Address High Part(0x7C)" > > register to support 64 bits dma dram address. > > Add helper routines functions to compute the dma dram address, new > > fe

RE: [PATCH v4 08/16] aspeed/smc: support 64 bits dma dram address

Hi Cedric, > On 5/27/24 10:02, Jamin Lin wrote: > > AST2700 support the maximum dram size is 8GiB and has a "DMA DRAM > Side > > Address High Part(0x7C)" > > register to support 64 bits dma dram address. > > Add helper routines functions to compute the dma dram address, new > > features and update

Re: [PATCH v4 08/16] aspeed/smc: support 64 bits dma dram address

Hi Jamin, On 27/5/24 10:02, Jamin Lin wrote: AST2700 support the maximum dram size is 8GiB and has a "DMA DRAM Side Address High Part(0x7C)" register to support 64 bits dma dram address. Add helper routines functions to compute the dma dram address, new features and update trace-event to support

Re: [PATCH v4 08/16] aspeed/smc: support 64 bits dma dram address

On 5/27/24 10:02, Jamin Lin wrote: AST2700 support the maximum dram size is 8GiB and has a "DMA DRAM Side Address High Part(0x7C)" register to support 64 bits dma dram address. Add helper routines functions to compute the dma dram address, new features and update trace-event to support 64 bits dr

[PATCH v4 08/16] aspeed/smc: support 64 bits dma dram address

AST2700 support the maximum dram size is 8GiB and has a "DMA DRAM Side Address High Part(0x7C)" register to support 64 bits dma dram address. Add helper routines functions to compute the dma dram address, new features and update trace-event to support 64 bits dram address. Signed-off-by: Troy Lee