Re: [PATCH v4 1/3] target/riscv: smstateen check for fcsr

2023-05-17 Thread Alistair Francis
On Thu, May 18, 2023 at 12:49 PM Mayuresh Chitale wrote: > > On Wed, May 17, 2023 at 8:42 AM Alistair Francis wrote: > > > > On Tue, May 2, 2023 at 12:00 AM Mayuresh Chitale > > wrote: > > > > > > If smstateen is implemented and smtateen0.fcsr is clear and misa.F > > > is off then the floating p

Re: [PATCH v4 1/3] target/riscv: smstateen check for fcsr

2023-05-17 Thread Mayuresh Chitale
On Wed, May 17, 2023 at 8:42 AM Alistair Francis wrote: > > On Tue, May 2, 2023 at 12:00 AM Mayuresh Chitale > wrote: > > > > If smstateen is implemented and smtateen0.fcsr is clear and misa.F > > is off then the floating point operations must return illegal > > instruction exception or virtual i

Re: [PATCH v4 1/3] target/riscv: smstateen check for fcsr

2023-05-16 Thread Alistair Francis
On Tue, May 2, 2023 at 12:00 AM Mayuresh Chitale wrote: > > If smstateen is implemented and smtateen0.fcsr is clear and misa.F > is off then the floating point operations must return illegal > instruction exception or virtual instruction trap, if relevant. Do you mind re-wording this commit messa

[PATCH v4 1/3] target/riscv: smstateen check for fcsr

2023-05-01 Thread Mayuresh Chitale
If smstateen is implemented and smtateen0.fcsr is clear and misa.F is off then the floating point operations must return illegal instruction exception or virtual instruction trap, if relevant. Signed-off-by: Mayuresh Chitale Reviewed-by: Weiwei Li --- target/riscv/csr.c | 15 +++ 1