The initial PMU support were made under the assumption that the counters would be set before running the PMU and read after either freezing the PMU manually or via a performance monitor alert.
Turns out that some EBB powerpc kernel tests set the counters after unfreezing the counters. Setting a PMC value when the PMU is running means that, at that moment, the baseline for calculating cycle events needs to be updated. Updating this baseline means that we need to update all the PMCs with their actual value at that moment. Any existing counter negative timer needs to be discarded an a new one, with the updated values, must be set again. This patch does that via a new 'helper_store_pmc()' that is called in the mtspr() callbacks of PMU counters. Signed-off-by: Daniel Henrique Barboza <danielhb...@gmail.com> --- target/ppc/cpu_init.c | 12 ++++++------ target/ppc/helper.h | 1 + target/ppc/power8-pmu-regs.c.inc | 17 ++++++++++++++++- target/ppc/power8-pmu.c | 18 ++++++++++++++++++ target/ppc/spr_tcg.h | 1 + 5 files changed, 42 insertions(+), 7 deletions(-) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index eb1a0320b9..cf68e2c5a7 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -6832,27 +6832,27 @@ static void register_book3s_pmu_sup_sprs(CPUPPCState *env) KVM_REG_PPC_MMCRA, 0x00000000); spr_register_kvm(env, SPR_POWER_PMC1, "PMC1", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_generic, &spr_write_PMC, KVM_REG_PPC_PMC1, 0x00000000); spr_register_kvm(env, SPR_POWER_PMC2, "PMC2", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_generic, &spr_write_PMC, KVM_REG_PPC_PMC2, 0x00000000); spr_register_kvm(env, SPR_POWER_PMC3, "PMC3", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_generic, &spr_write_PMC, KVM_REG_PPC_PMC3, 0x00000000); spr_register_kvm(env, SPR_POWER_PMC4, "PMC4", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_generic, &spr_write_PMC, KVM_REG_PPC_PMC4, 0x00000000); spr_register_kvm(env, SPR_POWER_PMC5, "PMC5", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_generic, &spr_write_PMC, KVM_REG_PPC_PMC5, 0x00000000); spr_register_kvm(env, SPR_POWER_PMC6, "PMC6", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_generic, &spr_write_PMC, KVM_REG_PPC_PMC6, 0x00000000); spr_register_kvm(env, SPR_POWER_SIAR, "SIAR", SPR_NOACCESS, SPR_NOACCESS, diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 5814e2f251..b0ebfaff51 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -22,6 +22,7 @@ DEF_HELPER_2(store_lpcr, void, env, tl) DEF_HELPER_2(store_pcr, void, env, tl) DEF_HELPER_2(store_mmcr0, void, env, tl) DEF_HELPER_2(store_mmcr1, void, env, tl) +DEF_HELPER_3(store_pmc, void, env, i32, i64) DEF_HELPER_2(insns_inc, void, env, i32) #endif DEF_HELPER_1(check_tlb_flush_local, void, env) diff --git a/target/ppc/power8-pmu-regs.c.inc b/target/ppc/power8-pmu-regs.c.inc index f8ca44cfdc..8a9e1f41ef 100644 --- a/target/ppc/power8-pmu-regs.c.inc +++ b/target/ppc/power8-pmu-regs.c.inc @@ -212,13 +212,23 @@ void spr_read_PMC56_ureg(DisasContext *ctx, int gprn, int sprn) spr_read_PMC14_ureg(ctx, gprn, sprn); } +void spr_write_PMC(DisasContext *ctx, int sprn, int gprn) +{ + TCGv_i32 t_sprn = tcg_const_i32(sprn); + + gen_icount_io_start(ctx); + gen_helper_store_pmc(cpu_env, t_sprn, cpu_gpr[gprn]); + + tcg_temp_free_i32(t_sprn); +} + void spr_write_PMC14_ureg(DisasContext *ctx, int sprn, int gprn) { if (!spr_groupA_write_allowed(ctx)) { return; } - spr_write_ureg(ctx, sprn, gprn); + spr_write_PMC(ctx, sprn + 0x10, gprn); } void spr_write_PMC56_ureg(DisasContext *ctx, int sprn, int gprn) @@ -302,4 +312,9 @@ void spr_write_MMCR1(DisasContext *ctx, int sprn, int gprn) { spr_write_generic(ctx, sprn, gprn); } + +void spr_write_PMC(DisasContext *ctx, int sprn, int gprn) +{ + spr_write_generic(ctx, sprn, gprn); +} #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c index 3946314e9c..3fc09cebe4 100644 --- a/target/ppc/power8-pmu.c +++ b/target/ppc/power8-pmu.c @@ -343,4 +343,22 @@ void cpu_ppc_pmu_init(CPUPPCState *env) } } +void helper_store_pmc(CPUPPCState *env, uint32_t sprn, uint64_t value) +{ + bool pmu_frozen = env->spr[SPR_POWER_MMCR0] & MMCR0_FC; + + if (pmu_frozen) { + env->spr[sprn] = value; + return; + } + + /* + * Update counters with the events counted so far, define + * the new value of the PMC and start a new cycle count + * session. + */ + pmu_events_update_cycles(env); + env->spr[sprn] = value; + start_cycle_count_session(env); +} #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ diff --git a/target/ppc/spr_tcg.h b/target/ppc/spr_tcg.h index 28126da6e2..01fded3c15 100644 --- a/target/ppc/spr_tcg.h +++ b/target/ppc/spr_tcg.h @@ -28,6 +28,7 @@ void spr_write_generic(DisasContext *ctx, int sprn, int gprn); void spr_write_MMCR0(DisasContext *ctx, int sprn, int gprn); void spr_write_MMCR1(DisasContext *ctx, int sprn, int gprn); void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn); +void spr_write_PMC(DisasContext *ctx, int sprn, int gprn); void spr_read_xer(DisasContext *ctx, int gprn, int sprn); void spr_write_xer(DisasContext *ctx, int sprn, int gprn); void spr_read_lr(DisasContext *ctx, int gprn, int sprn); -- 2.31.1