On Thu, May 26, 2022 at 7:07 PM Alistair Francis wrote:
>
> On Thu, May 26, 2022 at 5:16 PM Atish Patra wrote:
> >
> > On Wed, May 25, 2022 at 10:11 PM Alistair Francis
> > wrote:
> > >
> > > On Sat, May 14, 2022 at 4:39 AM Atish Patra wrote:
> > > >
> > > > stimecmp allows the supervisor
On Thu, May 26, 2022 at 5:16 PM Atish Patra wrote:
>
> On Wed, May 25, 2022 at 10:11 PM Alistair Francis
> wrote:
> >
> > On Sat, May 14, 2022 at 4:39 AM Atish Patra wrote:
> > >
> > > stimecmp allows the supervisor mode to update stimecmp CSR directly
> > > to program the next timer
On Wed, May 25, 2022 at 10:11 PM Alistair Francis wrote:
>
> On Sat, May 14, 2022 at 4:39 AM Atish Patra wrote:
> >
> > stimecmp allows the supervisor mode to update stimecmp CSR directly
> > to program the next timer interrupt. This CSR is part of the Sstc
> > extension which was ratified
On Sat, May 14, 2022 at 4:39 AM Atish Patra wrote:
>
> stimecmp allows the supervisor mode to update stimecmp CSR directly
> to program the next timer interrupt. This CSR is part of the Sstc
> extension which was ratified recently.
>
> Signed-off-by: Atish Patra
> ---
> target/riscv/cpu.c
stimecmp allows the supervisor mode to update stimecmp CSR directly
to program the next timer interrupt. This CSR is part of the Sstc
extension which was ratified recently.
Signed-off-by: Atish Patra
---
target/riscv/cpu.c | 8
target/riscv/cpu.h | 7 +++
