Re: [PATCH v5 03/18] hw/arm/smmuv3: Fix encoding of CLASS in events

2024-07-17 Thread Eric Auger
On 7/17/24 17:58, Jean-Philippe Brucker wrote: > Hi Eric, > > On Wed, Jul 17, 2024 at 05:07:57PM +0200, Eric Auger wrote: >> Hi Jean, >> >> On 7/15/24 10:45, Mostafa Saleh wrote: >>> The SMMUv3 spec (ARM IHI 0070 F.b - 7.3 Event records) defines the >>> class of events faults as: >>> >>> CLASS:

Re: [PATCH v5 03/18] hw/arm/smmuv3: Fix encoding of CLASS in events

2024-07-17 Thread Jean-Philippe Brucker
Hi Eric, On Wed, Jul 17, 2024 at 05:07:57PM +0200, Eric Auger wrote: > Hi Jean, > > On 7/15/24 10:45, Mostafa Saleh wrote: > > The SMMUv3 spec (ARM IHI 0070 F.b - 7.3 Event records) defines the > > class of events faults as: > > > > CLASS: The class of the operation that caused the fault: > > - 0

Re: [PATCH v5 03/18] hw/arm/smmuv3: Fix encoding of CLASS in events

2024-07-17 Thread Eric Auger
Hi Jean, On 7/15/24 10:45, Mostafa Saleh wrote: > The SMMUv3 spec (ARM IHI 0070 F.b - 7.3 Event records) defines the > class of events faults as: > > CLASS: The class of the operation that caused the fault: > - 0b00: CD, CD fetch. > - 0b01: TTD, Stage 1 translation table fetch. > - 0b10: IN, Input

[PATCH v5 03/18] hw/arm/smmuv3: Fix encoding of CLASS in events

2024-07-15 Thread Mostafa Saleh
The SMMUv3 spec (ARM IHI 0070 F.b - 7.3 Event records) defines the class of events faults as: CLASS: The class of the operation that caused the fault: - 0b00: CD, CD fetch. - 0b01: TTD, Stage 1 translation table fetch. - 0b10: IN, Input address However, this value was not set and left as 0 which