This register is present for either VHE or Debugv8p2.
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
---
v3: Rely on EL3-no-EL2 squashing during registration.
---
target/arm/helper.c | 15 +++++++++++----
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 72d05070f0..7b31c71980 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -7246,11 +7246,14 @@ static const ARMCPRegInfo jazelle_regs[] = {
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
};
+static const ARMCPRegInfo contextidr_el2 = {
+ .name = "CONTEXTIDR_EL2", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 1,
+ .access = PL2_RW,
+ .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[2])
+};
+
static const ARMCPRegInfo vhe_reginfo[] = {
- { .name = "CONTEXTIDR_EL2", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 1,
- .access = PL2_RW,
- .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[2]) },
{ .name = "TTBR1_EL2", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 1,
.access = PL2_RW, .writefn = vmsa_tcr_ttbr_el2_write,
@@ -8215,6 +8218,10 @@ void register_cp_regs_for_features(ARMCPU *cpu)
define_one_arm_cp_reg(cpu, &ssbs_reginfo);
}
+ if (cpu_isar_feature(aa64_vh, cpu) ||
+ cpu_isar_feature(aa64_debugv8p2, cpu)) {
+ define_one_arm_cp_reg(cpu, &contextidr_el2);
+ }
if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu)) {
define_arm_cp_regs(cpu, vhe_reginfo);
}
--
2.34.1
