Re: [PATCH v5 2/4] target/riscv/pmp.c: Fix the index offset on RV64

2020-07-27 Thread Alistair Francis
On Sat, Jul 25, 2020 at 8:04 AM Zong Li wrote: > > On RV64, the reg_index is 2 (pmpcfg2 CSR) after the seventh pmp > entry, it is not 1 (pmpcfg1 CSR) like RV32. In the original > implementation, the second parameter of pmp_write_cfg is > "reg_index * sizeof(target_ulong)", and we get the the resul

Re: [PATCH v5 2/4] target/riscv/pmp.c: Fix the index offset on RV64

2020-07-27 Thread Bin Meng
On Sat, Jul 25, 2020 at 11:03 PM Zong Li wrote: > > On RV64, the reg_index is 2 (pmpcfg2 CSR) after the seventh pmp > entry, it is not 1 (pmpcfg1 CSR) like RV32. In the original > implementation, the second parameter of pmp_write_cfg is > "reg_index * sizeof(target_ulong)", and we get the the resu

[PATCH v5 2/4] target/riscv/pmp.c: Fix the index offset on RV64

2020-07-25 Thread Zong Li
On RV64, the reg_index is 2 (pmpcfg2 CSR) after the seventh pmp entry, it is not 1 (pmpcfg1 CSR) like RV32. In the original implementation, the second parameter of pmp_write_cfg is "reg_index * sizeof(target_ulong)", and we get the the result which is started from 16 if reg_index is 2, but we expec