Re: [PATCH v6 04/61] target/riscv: add vector configure instruction

On 2020/3/23 14:51, Kito Cheng wrote: Hi Zhiwei: vsetvl and vsetvli seems like missing ISA checking before translate, this cause those 2 instructions can be executed even RVV not enable. My testing env is qemu riscv64-linux-user mode. Hi Kito, I think you are right. Thanks for pointing

Re: [PATCH v6 04/61] target/riscv: add vector configure instruction

Hi Zhiwei: vsetvl and vsetvli seems like missing ISA checking before translate, this cause those 2 instructions can be executed even RVV not enable. My testing env is qemu riscv64-linux-user mode. > diff --git a/target/riscv/insn_trans/trans_rvv.inc.c > b/target/riscv/insn_trans/trans_rvv.inc.c

[PATCH v6 04/61] target/riscv: add vector configure instruction

vsetvl and vsetvli are two configure instructions for vl, vtype. TB flags should update after configure instructions. The (ill, lmul, sew ) of vtype and the bit of (VSTART == 0 && VL == VLMAX) will be placed within tb_flags. Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: