Re: [PATCH v6 09/61] target/riscv: add vector amo operations

On 3/17/20 8:06 AM, LIU Zhiwei wrote: > Vector AMOs operate as if aq and rl bits were zero on each element > with regard to ordering relative to other instructions in the same hart. > Vector AMOs provide no ordering guarantee between element operations > in the same vector AMO instruction > > Sign

Re: [PATCH v6 09/61] target/riscv: add vector amo operations

On Tue, Mar 17, 2020 at 8:25 AM LIU Zhiwei wrote: > > Vector AMOs operate as if aq and rl bits were zero on each element > with regard to ordering relative to other instructions in the same hart. > Vector AMOs provide no ordering guarantee between element operations > in the same vector AMO instru

[PATCH v6 09/61] target/riscv: add vector amo operations

Vector AMOs operate as if aq and rl bits were zero on each element with regard to ordering relative to other instructions in the same hart. Vector AMOs provide no ordering guarantee between element operations in the same vector AMO instruction Signed-off-by: LIU Zhiwei --- target/riscv/helper.h