Re: [PATCH v6 13/25] target/riscv: Introduce mmuidx_priv

2023-04-10 Thread Alistair Francis
On Sat, Mar 25, 2023 at 9:53 PM Richard Henderson wrote: > > Use the priv level encoded into the mmu_idx, rather than > starting from env->priv. We have already checked MPRV+MPP > in riscv_cpu_mmu_index -- no need to repeat that. > > Signed-off-by: Richard Henderson Reviewed-by: Alistair Franci

Re: [PATCH v6 13/25] target/riscv: Introduce mmuidx_priv

2023-03-28 Thread Richard Henderson
On 3/27/23 18:54, LIU Zhiwei wrote: Can we remove the PRIV from the tb flags after we have this function? No, because this is the priv of the memory operation as modified by e.g. MPRV, not the true cpu priv. For this implementation, we explicitly use the tb flags for mmu index. I think it is

Re: [PATCH v6 13/25] target/riscv: Introduce mmuidx_priv

2023-03-27 Thread LIU Zhiwei
On 2023/3/28 9:33, LIU Zhiwei wrote: On 2023/3/28 0:29, Richard Henderson wrote: On 3/26/23 19:07, LIU Zhiwei wrote: +static inline int mmuidx_priv(int mmu_idx) +{ +    int ret = mmu_idx & 3; +    if (ret == MMUIdx_S_SUM) { +    ret = PRV_S; +    } +    return ret; +} + Can we remove t

Re: [PATCH v6 13/25] target/riscv: Introduce mmuidx_priv

2023-03-27 Thread LIU Zhiwei
On 2023/3/28 0:29, Richard Henderson wrote: On 3/26/23 19:07, LIU Zhiwei wrote: +static inline int mmuidx_priv(int mmu_idx) +{ +    int ret = mmu_idx & 3; +    if (ret == MMUIdx_S_SUM) { +    ret = PRV_S; +    } +    return ret; +} + Can we remove the PRIV from the tb flags after we have

Re: [PATCH v6 13/25] target/riscv: Introduce mmuidx_priv

2023-03-27 Thread Richard Henderson
On 3/26/23 19:07, LIU Zhiwei wrote: +static inline int mmuidx_priv(int mmu_idx) +{ +    int ret = mmu_idx & 3; +    if (ret == MMUIdx_S_SUM) { +    ret = PRV_S; +    } +    return ret; +} + Can we remove the PRIV from the tb flags after we have this function? No, because this is the priv

Re: [PATCH v6 13/25] target/riscv: Introduce mmuidx_priv

2023-03-26 Thread LIU Zhiwei
On 2023/3/25 18:54, Richard Henderson wrote: Use the priv level encoded into the mmu_idx, rather than starting from env->priv. We have already checked MPRV+MPP in riscv_cpu_mmu_index -- no need to repeat that. Signed-off-by: Richard Henderson --- target/riscv/internals.h | 9 + t

[PATCH v6 13/25] target/riscv: Introduce mmuidx_priv

2023-03-25 Thread Richard Henderson
Use the priv level encoded into the mmu_idx, rather than starting from env->priv. We have already checked MPRV+MPP in riscv_cpu_mmu_index -- no need to repeat that. Signed-off-by: Richard Henderson --- target/riscv/internals.h | 9 + target/riscv/cpu_helper.c | 6 +- 2 files change