[PATCH v6 17/22] target/riscv: Remove VILL field in VTYPE

[LIU Zhiwei]

Signed-off-by: LIU Zhiwei <zhiwei_...@c-sky.com>
Acked-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
---
 target/riscv/cpu.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 645a1b3f6c..85eb5c63cf 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -110,7 +110,6 @@ FIELD(VTYPE, VTA, 6, 1)
 FIELD(VTYPE, VMA, 7, 1)
 FIELD(VTYPE, VEDIV, 8, 2)
 FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11)
-FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1)
 
 struct CPURISCVState {
     target_ulong gpr[32];
-- 
2.25.1