Re: [PATCH v6 61/61] target/riscv: configure and turn on vector extension from command line

2020-03-27 Thread Richard Henderson
On 3/17/20 8:06 AM, LIU Zhiwei wrote: > Vector extension is default off. The only way to use vector extension is > 1. use cpu rv32 or rv64 > 2. turn on it by command line > "-cpu rv64,x-v=true,vlen=128,elen=64,vext_spec=v0.7.1". > > vlen is the vector register length, default value is 128 bit. >

Re: [PATCH v6 61/61] target/riscv: configure and turn on vector extension from command line

2020-03-25 Thread Alistair Francis
On Tue, Mar 17, 2020 at 10:09 AM LIU Zhiwei wrote: > > Vector extension is default off. The only way to use vector extension is > 1. use cpu rv32 or rv64 > 2. turn on it by command line > "-cpu rv64,x-v=true,vlen=128,elen=64,vext_spec=v0.7.1". > > vlen is the vector register length, default value

[PATCH v6 61/61] target/riscv: configure and turn on vector extension from command line

2020-03-17 Thread LIU Zhiwei
Vector extension is default off. The only way to use vector extension is 1. use cpu rv32 or rv64 2. turn on it by command line "-cpu rv64,x-v=true,vlen=128,elen=64,vext_spec=v0.7.1". vlen is the vector register length, default value is 128 bit. elen is the max operator size in bits, default value