Hi Xiaoyao,
On Mon, Jan 15, 2024 at 12:27:43PM +0800, Xiaoyao Li wrote:
> Date: Mon, 15 Jan 2024 12:27:43 +0800
> From: Xiaoyao Li
> Subject: Re: [PATCH v7 15/16] i386: Use offsets get NumSharingCache for
> CPUID[0x801D].EAX[bits 25:14]
>
> On 1/15/2024 11:48 AM, Zhao
On 1/15/2024 11:48 AM, Zhao Liu wrote:
Hi Xiaoyao,
On Sun, Jan 14, 2024 at 10:42:41PM +0800, Xiaoyao Li wrote:
Date: Sun, 14 Jan 2024 22:42:41 +0800
From: Xiaoyao Li
Subject: Re: [PATCH v7 15/16] i386: Use offsets get NumSharingCache for
CPUID[0x801D].EAX[bits 25:14]
On 1/8/2024 4:27
Hi Xiaoyao,
On Sun, Jan 14, 2024 at 10:42:41PM +0800, Xiaoyao Li wrote:
> Date: Sun, 14 Jan 2024 22:42:41 +0800
> From: Xiaoyao Li
> Subject: Re: [PATCH v7 15/16] i386: Use offsets get NumSharingCache for
> CPUID[0x801D].EAX[bits 25:14]
>
> On 1/8/2024 4:27 PM, Zhao L
On 1/8/2024 4:27 PM, Zhao Liu wrote:
From: Zhao Liu
The commit 8f4202fb1080 ("i386: Populate AMD Processor Cache Information
for cpuid 0x801D") adds the cache topology for AMD CPU by encoding
the number of sharing threads directly.
From AMD's APM, NumSharingCache
From: Zhao Liu
The commit 8f4202fb1080 ("i386: Populate AMD Processor Cache Information
for cpuid 0x801D") adds the cache topology for AMD CPU by encoding
the number of sharing threads directly.
>From AMD's APM, NumSharingCache (CPUID[0x801D].EAX[bits 25:14])
means [1]:
The number of
