Hi,
We had problems right at the finish line of the pull request due to endianness
problems reported in the Gitlab CI [1]. This triggered discussions in the
middle of the pull request patches [2] that resulted in this new version.
We dealt with the endianness problem that was hitting the Gitlab CI in s390x.
It was a mix of test changes required in the libqos support, a solution
proposed by Peter, and a real endianness problem in patch 3. I made sure to
test this version in a s390x VM and everything seems good.
Another change made, after review comments from Peter, was the removal of all
locks that were result of the old threading approach that we abandoned in v3.
BQL is proven to be enough, at least in my testing, to prevent race conditions.
Nothing is stopping us from changing our minds later, and even rollback to a
thread model with spinlocks and so on, but for now we'll stick to what we
decided back in v3.
The rest were punctual changes also requested by Peter and Tomasz during the
discussions in the pull request [1].
Patches based on riscv-to-apply.next. All patches acked.
Changes from v7:
- patch 3:
- fixed Copyright text of added files
- all functions starting with '__X' were renamed to 'riscv_iommu_X'
- removed qemu/osdep.h from riscv-iommu.h
- removed unused '__rfu' attribute from RISCVIOMMUContext
- removed core_lock, ctx_lock and regs_lock
- converted the 'read page table entry' code from using dma_memory_read() and
le_to_cpu() to use ldl_le_dma()
- replaced the 'if size' chain for 'ldn_le_p()' in riscv_iommu_mmio_read()
- added a new riscv_iommu_write_reg_val() helper. Used it to remove the 'if
size' chains inside riscv_iommu_mmio_write()
- do le64_to_cpu() before using 'val' in riscv_iommu_mmio_write() ICVEC/IPSR
path;
- use brackets to wrap around (icvec & bit) in riscv_iommu_get_icvec_vector()
- patch 5:
- fixed Copyright text of riscv-iommu-pci.c
- patch 7:
- use qpci_io_read(l/q) instead of qcpi_memread()
- patch 8:
- remove iot_lock
- remove unused '__rfu' attribute from RISCVIOMMUEntry
- all functions starting with '__X' were renamed to 'riscv_iommu_X'
- patch 11:
- use qpci_io_write(l/q) instead of qpci_memwrite()
- v7 link:
https://lore.kernel.org/qemu-riscv/20240903201633.93182-1-dbarb...@ventanamicro.com/
[1]
https://lore.kernel.org/qemu-devel/CAFEAcA_8A=8q8afspwy177x6q3rlos-kohwyudhtbpojnjl...@mail.gmail.com/
[2]
https://lore.kernel.org/qemu-devel/cafeaca8rdfyacfkdjga72wa4et9nfrwroifdbtydbxy6g6u...@mail.gmail.com/
Daniel Henrique Barboza (4):
pci-ids.rst: add Red Hat pci-id for RISC-V IOMMU device
test/qtest: add riscv-iommu-pci tests
qtest/riscv-iommu-test: add init queues test
docs/specs: add riscv-iommu
Tomasz Jeznach (8):
exec/memtxattr: add process identifier to the transaction attributes
hw/riscv: add riscv-iommu-bits.h
hw/riscv: add RISC-V IOMMU base emulation
hw/riscv: add riscv-iommu-pci reference device
hw/riscv/virt.c: support for RISC-V IOMMU PCIDevice hotplug
hw/riscv/riscv-iommu: add Address Translation Cache (IOATC)
hw/riscv/riscv-iommu: add ATS support
hw/riscv/riscv-iommu: add DBG support
docs/specs/index.rst | 1 +
docs/specs/pci-ids.rst | 2 +
docs/specs/riscv-iommu.rst | 90 ++
docs/system/riscv/virt.rst | 13 +
hw/riscv/Kconfig | 4 +
hw/riscv/meson.build | 1 +
hw/riscv/riscv-iommu-bits.h | 421 ++++++
hw/riscv/riscv-iommu-pci.c | 202 +++
hw/riscv/riscv-iommu.c | 2396 ++++++++++++++++++++++++++++++
hw/riscv/riscv-iommu.h | 130 ++
hw/riscv/trace-events | 17 +
hw/riscv/trace.h | 1 +
hw/riscv/virt.c | 33 +-
include/exec/memattrs.h | 5 +
include/hw/pci/pci.h | 1 +
include/hw/riscv/iommu.h | 36 +
meson.build | 1 +
tests/qtest/libqos/meson.build | 4 +
tests/qtest/libqos/riscv-iommu.c | 76 +
tests/qtest/libqos/riscv-iommu.h | 101 ++
tests/qtest/meson.build | 1 +
tests/qtest/riscv-iommu-test.c | 210 +++
22 files changed, 3745 insertions(+), 1 deletion(-)
create mode 100644 docs/specs/riscv-iommu.rst
create mode 100644 hw/riscv/riscv-iommu-bits.h
create mode 100644 hw/riscv/riscv-iommu-pci.c
create mode 100644 hw/riscv/riscv-iommu.c
create mode 100644 hw/riscv/riscv-iommu.h
create mode 100644 hw/riscv/trace-events
create mode 100644 hw/riscv/trace.h
create mode 100644 include/hw/riscv/iommu.h
create mode 100644 tests/qtest/libqos/riscv-iommu.c
create mode 100644 tests/qtest/libqos/riscv-iommu.h
create mode 100644 tests/qtest/riscv-iommu-test.c
--
2.45.2
