On Fri, Oct 4, 2024 at 6:00 AM Daniel Henrique Barboza
wrote:
>
>
>
> On 10/4/24 5:33 AM, Andrew Jones wrote:
> > On Thu, Oct 03, 2024 at 11:36:00AM GMT, Tomasz Jeznach wrote:
> >> On Thu, Oct 3, 2024 at 6:06 AM Daniel Henrique Barboza
> >> wrote:
> >>>
> >>>
> >>>
> >>> On 10/3/24 6:26 AM, Andre
On 10/4/24 5:33 AM, Andrew Jones wrote:
On Thu, Oct 03, 2024 at 11:36:00AM GMT, Tomasz Jeznach wrote:
On Thu, Oct 3, 2024 at 6:06 AM Daniel Henrique Barboza
wrote:
On 10/3/24 6:26 AM, Andrew Jones wrote:
On Tue, Oct 01, 2024 at 10:02:58PM GMT, Daniel Henrique Barboza wrote:
...
+/*
+ *
On Thu, Oct 03, 2024 at 11:36:00AM GMT, Tomasz Jeznach wrote:
> On Thu, Oct 3, 2024 at 6:06 AM Daniel Henrique Barboza
> wrote:
> >
> >
> >
> > On 10/3/24 6:26 AM, Andrew Jones wrote:
> > > On Tue, Oct 01, 2024 at 10:02:58PM GMT, Daniel Henrique Barboza wrote:
> > > ...
> > >> +/*
> > >> + * RISCV
On Thu, Oct 3, 2024 at 6:06 AM Daniel Henrique Barboza
wrote:
>
>
>
> On 10/3/24 6:26 AM, Andrew Jones wrote:
> > On Tue, Oct 01, 2024 at 10:02:58PM GMT, Daniel Henrique Barboza wrote:
> > ...
> >> +/*
> >> + * RISCV IOMMU Address Translation Lookup - Page Table Walk
> >> + *
> >> + * Note: Code i
On Thu, Oct 03, 2024 at 10:06:11AM GMT, Daniel Henrique Barboza wrote:
>
>
> On 10/3/24 6:26 AM, Andrew Jones wrote:
> > On Tue, Oct 01, 2024 at 10:02:58PM GMT, Daniel Henrique Barboza wrote:
> > ...
> > > +/*
> > > + * RISCV IOMMU Address Translation Lookup - Page Table Walk
> > > + *
> > > + *
On 10/3/24 6:26 AM, Andrew Jones wrote:
On Tue, Oct 01, 2024 at 10:02:58PM GMT, Daniel Henrique Barboza wrote:
...
+/*
+ * RISCV IOMMU Address Translation Lookup - Page Table Walk
+ *
+ * Note: Code is based on get_physical_address() from target/riscv/cpu_helper.c
+ * Both implementation can
On Tue, Oct 01, 2024 at 10:02:58PM GMT, Daniel Henrique Barboza wrote:
...
> +/*
> + * RISCV IOMMU Address Translation Lookup - Page Table Walk
> + *
> + * Note: Code is based on get_physical_address() from
> target/riscv/cpu_helper.c
> + * Both implementation can be merged into single helper func
From: Tomasz Jeznach
The RISC-V IOMMU specification is now ratified as-per the RISC-V
international process. The latest frozen specifcation can be found at:
https://github.com/riscv-non-isa/riscv-iommu/releases/download/v1.0/riscv-iommu.pdf
Add the foundation of the device emulation for RISC-V