On 3/7/23 10:39, David Woodhouse wrote:
On Tue, 2023-03-07 at 10:36 -0300, Daniel Henrique Barboza wrote:
Checkpatch will nag about it claiming that we need spaces between
'*'. The maintainer can fix it in-tree though.
I saw that and explicitly didn't care. 3/5 of the existing examples
wit
On Tue, 7 Mar 2023, Daniel Henrique Barboza wrote:
On 3/7/23 08:42, BALATON Zoltan wrote:
From: David Woodhouse
Back in the mists of time, before EISA came along and required per-pin
level control in the ELCR register, the i8259 had a single chip-wide
level-mode control in bit 3 of ICW1.
Even
On Tue, 2023-03-07 at 10:36 -0300, Daniel Henrique Barboza wrote:
>
> Checkpatch will nag about it claiming that we need spaces between
> '*'. The maintainer can fix it in-tree though.
I saw that and explicitly didn't care. 3/5 of the existing examples
within the tree look like that one — which i
On Tue, 7 Mar 2023 at 13:36, Daniel Henrique Barboza
wrote:
> On 3/7/23 08:42, BALATON Zoltan wrote:
> > @@ -168,6 +186,10 @@ static const VMStateDescription vmstate_pic_common = {
> > VMSTATE_UINT8(single_mode, PICCommonState),
> > VMSTATE_UINT8(elcr, PICCommonState),
> >
On 3/7/23 08:42, BALATON Zoltan wrote:
From: David Woodhouse
Back in the mists of time, before EISA came along and required per-pin
level control in the ELCR register, the i8259 had a single chip-wide
level-mode control in bit 3 of ICW1.
Even in the PIIX3 datasheet from 1996 this is documen
From: David Woodhouse
Back in the mists of time, before EISA came along and required per-pin
level control in the ELCR register, the i8259 had a single chip-wide
level-mode control in bit 3 of ICW1.
Even in the PIIX3 datasheet from 1996 this is documented as 'This bit is
disabled', but apparentl
