From: Alistair Francis <alistair.fran...@wdc.com>
Signed-off-by: Alistair Francis <alistair.fran...@wdc.com>
Reviewed-by: Chih-Min Chao <chihmin.c...@sifive.com>
Reviewed-by: Palmer Dabbelt <pal...@sifive.com>
Signed-off-by: Palmer Dabbelt <palmerdabb...@google.com>
---
target/riscv/cpu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 95de9e58a2..010125efd6 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -67,6 +67,7 @@
#define RVC RV('C')
#define RVS RV('S')
#define RVU RV('U')
+#define RVH RV('H')
/* S extension denotes that Supervisor mode exists, however it is possible
to have a core that support S mode but does not have an MMU and there
--
2.25.0.265.gbab2e86ba0-goog
