From: Bin Meng <bmeng...@gmail.com> It's Core *Local* Interruptor, not 'Level'.
Signed-off-by: Bin Meng <bmeng...@gmail.com> Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> Message-id: 20210627142816.19789-1-bmeng...@gmail.com Signed-off-by: Alistair Francis <alistair.fran...@wdc.com> --- docs/system/riscv/sifive_u.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/system/riscv/sifive_u.rst b/docs/system/riscv/sifive_u.rst index 32d0a1b85d..01108b5ecc 100644 --- a/docs/system/riscv/sifive_u.rst +++ b/docs/system/riscv/sifive_u.rst @@ -11,7 +11,7 @@ The ``sifive_u`` machine supports the following devices: * 1 E51 / E31 core * Up to 4 U54 / U34 cores -* Core Level Interruptor (CLINT) +* Core Local Interruptor (CLINT) * Platform-Level Interrupt Controller (PLIC) * Power, Reset, Clock, Interrupt (PRCI) * L2 Loosely Integrated Memory (L2-LIM) -- 2.31.1
