On 6/21/23 17:18, Frederic Barrat wrote:
On 21/06/2023 09:18, Cédric Le Goater wrote:
The XIVE2 TM ops are implemented with a shortcut (See the TODO in
pnv_xive2_tm_*()). We could
1. extend xive_tctx_tm_write/read with a 'bool gen1_tima_os' parameter:
xive_tctx_tm_write(xptr, tctx, offs
On 21/06/2023 09:18, Cédric Le Goater wrote:
The XIVE2 TM ops are implemented with a shortcut (See the TODO in
pnv_xive2_tm_*()). We could
1. extend xive_tctx_tm_write/read with a 'bool gen1_tima_os' parameter:
xive_tctx_tm_write(xptr, tctx, offset, value, size, gen1_tima_os);
and
On 6/20/23 16:31, Frederic Barrat wrote:
On 20/06/2023 13:20, Cédric Le Goater wrote:
On 6/20/23 12:45, Peter Maydell wrote:
On Sat, 10 Jun 2023 at 14:31, Daniel Henrique Barboza
wrote:
From: Frederic Barrat
The Thread Interrupt Management Area (TIMA) can be accessed through 4
ports, tar
On 6/20/23 16:31, Frederic Barrat wrote:
On 20/06/2023 13:20, Cédric Le Goater wrote:
On 6/20/23 12:45, Peter Maydell wrote:
On Sat, 10 Jun 2023 at 14:31, Daniel Henrique Barboza
wrote:
From: Frederic Barrat
The Thread Interrupt Management Area (TIMA) can be accessed through 4
ports, tar
On 20/06/2023 13:20, Cédric Le Goater wrote:
On 6/20/23 12:45, Peter Maydell wrote:
On Sat, 10 Jun 2023 at 14:31, Daniel Henrique Barboza
wrote:
From: Frederic Barrat
The Thread Interrupt Management Area (TIMA) can be accessed through 4
ports, targeted by the address. The base address of
On 6/20/23 12:45, Peter Maydell wrote:
On Sat, 10 Jun 2023 at 14:31, Daniel Henrique Barboza
wrote:
From: Frederic Barrat
The Thread Interrupt Management Area (TIMA) can be accessed through 4
ports, targeted by the address. The base address of a TIMA
is using port 0 and the other ports are 0
On Sat, 10 Jun 2023 at 14:31, Daniel Henrique Barboza
wrote:
>
> From: Frederic Barrat
>
> The Thread Interrupt Management Area (TIMA) can be accessed through 4
> ports, targeted by the address. The base address of a TIMA
> is using port 0 and the other ports are 0x80 apart. Using one port or
> a
From: Frederic Barrat
The Thread Interrupt Management Area (TIMA) can be accessed through 4
ports, targeted by the address. The base address of a TIMA
is using port 0 and the other ports are 0x80 apart. Using one port or
another can be useful to balance the load on the snoop buses. With
skiboot a
