From: Emmanuel Blot <emmanuel.b...@sifive.com> When no MMU is used and the guest code attempts to fetch an instruction from an invalid memory location, the exception index defaults to a data load access fault, rather an instruction access fault.
Signed-off-by: Emmanuel Blot <emmanuel.b...@sifive.com> Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> Message-id: fb9ea197-b018-4879-ab0f-922c2047a...@sifive.com Signed-off-by: Alistair Francis <alistair.fran...@wdc.com> --- target/riscv/cpu_helper.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 659ca8a173..1018c0036d 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -694,8 +694,10 @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, if (access_type == MMU_DATA_STORE) { cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT; - } else { + } else if (access_type == MMU_DATA_LOAD) { cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT; + } else { + cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT; } env->badaddr = addr; -- 2.31.1