[PULL 37/59] target/riscv: Allow debugger to access user timer and counter CSRs

[Palmer Dabbelt]

From: Bin Meng <bm...@tinylab.org>

At present user timer and counter CSRs are not reported in the
CSR XML hence gdb cannot access them.

Fix it by adding a debugger check in their predicate() routine.

Signed-off-by: Bin Meng <bm...@tinylab.org>
Reviewed-by: Weiwei Li <liwei...@iscas.ac.cn>
Reviewed-by: LIU Zhiwei <zhiwei_...@linux.alibaba.com>
Message-ID: <20230228104035.1879882-14-bm...@tinylab.org>
Signed-off-by: Palmer Dabbelt <pal...@rivosinc.com>
---
 target/riscv/csr.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 7284fd8a0d..10ae5df5e6 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -131,6 +131,10 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
 
 skip_ext_pmu_check:
 
+    if (env->debugger) {
+        return RISCV_EXCP_NONE;
+    }
+
     if (env->priv < PRV_M && !get_field(env->mcounteren, ctr_mask)) {
         return RISCV_EXCP_ILLEGAL_INST;
     }
-- 
2.39.2