On Tue, May 29, 2007 at 12:15:01AM +0200, Aurelien Jarno wrote:
Hi,
In the current implementation of the MIPS CPU, all instructions are
regarded as valid, being R1 or R2 instructions.
This patch fixes that by generating a reserved instruction exception
when an R2 instructions is decoded
Hi,
In the current implementation of the MIPS CPU, all instructions are
regarded as valid, being R1 or R2 instructions.
This patch fixes that by generating a reserved instruction exception
when an R2 instructions is decoded on an R1 only CPU.
Note that I have left the FPU code unchanged, as I
