Hello,
Sorry for my slow reply. I don't mind that, as long as I end up being
shown as the author in git. :) I've never committed from an email
before, so I'm not sure how that works. Does adding another "From: "
header in the body patch that up with git-am?
I don't know how much I'll be contri
On Wed, Apr 17, 2019 at 9:50 PM Daniel Santos wrote:
>
> In load_elf_binary, struct image_info interp_info is used without being
> properly initialized. One result is that when the ELF's program header
> doesn't contain an entry for the ABI flags, then the value of the struct
> image_info's fp_ab
Patchew URL:
https://patchew.org/QEMU/20190423092602.1254515-1-jakub.jer...@kernkonzept.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20190423092602.1254515-1-jakub.jer...@kernkonzept.com
Subject: [Qemu-devel
This commit addresses QEMU Bug #1825311:
mips_cpu_handle_mmu_fault renders all accessed pages executable
It allows finer-grained control over whether the accessed page should be
executable by moving the decision to the underlying map_address
function, which has more information for this.
As a
Patchew URL:
https://patchew.org/QEMU/20190423103855.1257968-1-jakub.jer...@kernkonzept.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20190423103855.1257968-1-jakub.jer...@kernkonzept.com
Subject: [Qemu-devel
This commit addresses QEMU Bug #1825311:
mips_cpu_handle_mmu_fault renders all accessed pages executable
It allows finer-grained control over whether the accessed page should be
executable by moving the decision to the underlying map_address
function, which has more information for this.
As a
In load_elf_binary, struct image_info interp_info is used without being
properly initialized. One result is that when the ELF's program header
doesn't contain an entry for the ABI flags, then the value of the struct
image_info's fp_abi field is set to whatever happened to be in stack
memory at the
BALATON Zoltan writes:
> On Tue, 19 Mar 2019, Paolo Bonzini wrote:
>> Do not create an ATI VGA if "-vga none" was passed on the command line.
>>
>> Cc: BALATON Zoltan
>
> Thanks, I did not know about this variable. Although the real hardware
> has the GPU soldered on the mainboard it makes sense
On Tue, 19 Mar 2019, Paolo Bonzini wrote:
Do not create an ATI VGA if "-vga none" was passed on the command line.
Cc: BALATON Zoltan
Thanks, I did not know about this variable. Although the real hardware has
the GPU soldered on the mainboard it makes sense to allow it to be
disabled in QEMU
> From: Paolo Bonzini
> Cc: phi...@redhat.com; BALATON Zoltan; Aleksandar Markovic; Aleksandar
> Rikalo; Aurelien Jarno
> Subject: [PATCH] mips-fulong2e: obey -vga none
>
> Do not create an ATI VGA if "-vga none" was passed on the command line.
>
> Cc: BALATON Zoltan
> Signed-off-by: Paolo Bon
Do not create an ATI VGA if "-vga none" was passed on the command line.
Cc: BALATON Zoltan
Signed-off-by: Paolo Bonzini
---
hw/mips/mips_fulong2e.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/hw/mips/mips_fulong2e.c b/hw/mips/mips_fulong2e.c
index 9d7480ed31..
> From: Aleksandar Markovic [mailto:amarko...@wavecomp.com]
> > From: Markus Armbruster
> > Subject: Re: [Qemu-devel] [PATCH] mips: implement qmp query-cpu-definitions
> > command
>
> > Please rebase. Let me know if you need help.
>
> Hi, Markus.
>
>
> From: Markus Armbruster
> Subject: Re: [Qemu-devel] [PATCH] mips: implement qmp query-cpu-definitions
> command
> Please rebase. Let me know if you need help.
Hi, Markus.
Pavel was probably busy today, so I took the liberty to rebase the patch,
and here is the v2:
https://l
Philippe Mathieu-Daudé writes:
> Hi Pavel,
>
> On 2/11/19 6:34 AM, Pavel Dovgalyuk wrote:
>> Ping.
>
> You forgot to Cc Aleksandar, to get his MIPS maintainer Ack-by:
>
> ./scripts/get_maintainer.pl -f target/mips/helper.c
> Aleksandar Markovic (maintainer:MIPS)
>
>>
>> Pavel Dovgalyuk
>>
>>>
> From: Aleksandar Markovic [mailto:amarko...@wavecomp.com]
> > From: Pavel Dovgalyuk [mailto:pavel.dovga...@ispras.ru]
> >
> > This patch enables QMP-based querying of the available CPU types for MIPS
> > and MIPS64 platforms.
> >
> > Signed-off-by: Pavel Dovgalyuk
> > ---
> > monitor.c
> From: Pavel Dovgalyuk [mailto:pavel.dovga...@ispras.ru]
> Sent: Tuesday, February 05, 2019 4:08 PM
> To: qemu-devel@nongnu.org
> Cc: pavel.dovga...@ispras.ru; arik...@wavecomp.com; mdr...@linux.vnet.ibm.com;
> arm...@redhat.com; dovga...@ispras.ru; natalia.furs...@ispras.ru;
> ebl...@redhat.com;
Hi Pavel,
On 2/11/19 6:34 AM, Pavel Dovgalyuk wrote:
> Ping.
You forgot to Cc Aleksandar, to get his MIPS maintainer Ack-by:
./scripts/get_maintainer.pl -f target/mips/helper.c
Aleksandar Markovic (maintainer:MIPS)
>
> Pavel Dovgalyuk
>
>> -Original Message-
>> From: Pavel Dovgalyuk
Ping.
Pavel Dovgalyuk
> -Original Message-
> From: Pavel Dovgalyuk [mailto:pavel.dovga...@ispras.ru]
> Sent: Tuesday, February 05, 2019 4:08 PM
> To: qemu-devel@nongnu.org
> Cc: pavel.dovga...@ispras.ru; arik...@wavecomp.com; mdr...@linux.vnet.ibm.com;
> arm...@redhat.com; dovga...@ispra
This patch enables QMP-based querying of the available CPU types for MIPS
and MIPS64 platforms.
Signed-off-by: Pavel Dovgalyuk
---
monitor.c|2 +-
target/mips/helper.c | 33 +
2 files changed, 34 insertions(+), 1 deletion(-)
diff --git a/monitor
On 19/09/2017 15:13, Eric Blake wrote:
> Although none of the existing macro call-sites were broken,
> it's always better to write macros that properly parenthesize
> arguments that can be complex expressions, so that the intended
> order of operations is not broken.
>
> Signed-off-by: Eric Blak
Although none of the existing macro call-sites were broken,
it's always better to write macros that properly parenthesize
arguments that can be complex expressions, so that the intended
order of operations is not broken.
Signed-off-by: Eric Blake
---
target/mips/dsp_helper.c | 56 +++
Currently the malta board is loading the initrd just after the kernel.
This doesn't work for kaslr enabled kernels, as the initrd ends-up being
overwritten.
Move the initrd at the end of the low memory, that should leave a
sufficient gap for kaslr.
Signed-off-by: Aurelien Jarno
---
hw/mips/mips
On 2017-05-02 15:03, Pavel Dovgalyuk wrote:
> From: Pavel Dovgalyuk
>
> This patch fixes setting DExcCode field of CP0 Debug register
> when SDBBP instruction is executed. According to EJTAG specification,
> this field must be set to the value 9 (Bp).
>
> Signed-off-by: Pavel Dovgalyuk
> ---
>
On 05/02/2017 09:03 AM, Pavel Dovgalyuk wrote:
From: Pavel Dovgalyuk
This patch fixes setting DExcCode field of CP0 Debug register
when SDBBP instruction is executed. According to EJTAG specification,
this field must be set to the value 9 (Bp).
Signed-off-by: Pavel Dovgalyuk
Reviewed-by: Ph
From: Pavel Dovgalyuk
This patch fixes setting DExcCode field of CP0 Debug register
when SDBBP instruction is executed. According to EJTAG specification,
this field must be set to the value 9 (Bp).
Signed-off-by: Pavel Dovgalyuk
---
target/mips/helper.c |2 ++
1 file changed, 2 insertions(
On 18/01/16 17:35, Peter Maydell wrote:
> Clean up includes so that osdep.h is included first and headers
> which it implies are not included manually.
>
> This commit was created with scripts/clean-includes.
>
> Signed-off-by: Peter Maydell
> ---
> disas/mips.c | 1 +
> hw/mips/add
Clean up includes so that osdep.h is included first and headers
which it implies are not included manually.
This commit was created with scripts/clean-includes.
Signed-off-by: Peter Maydell
---
disas/mips.c | 1 +
hw/mips/addr.c | 1 +
hw/mips/cputimer.c | 1 +
hw/mi
On 2015-06-15 10:48, Pavel Dovgaluk wrote:
> > From: Aurelien Jarno [mailto:aurel...@aurel32.net]
> > On 2015-06-15 07:53, Pavel Dovgaluk wrote:
> > > > From: Aurelien Jarno [mailto:aurel...@aurel32.net]
> > > > On 2015-06-10 11:33, Pavel Dovgalyuk wrote:
> > > > > This patch fixes exception handli
On 2015-06-15 10:39, Pavel Dovgaluk wrote:
> > From: Aurelien Jarno [mailto:aurel...@aurel32.net]
> > On 2015-06-15 07:53, Pavel Dovgaluk wrote:
> > > > From: Aurelien Jarno [mailto:aurel...@aurel32.net]
> > > > On 2015-06-10 11:33, Pavel Dovgalyuk wrote:
> > > > > This patch fixes exception handli
> From: Aurelien Jarno [mailto:aurel...@aurel32.net]
> On 2015-06-15 07:53, Pavel Dovgaluk wrote:
> > > From: Aurelien Jarno [mailto:aurel...@aurel32.net]
> > > On 2015-06-10 11:33, Pavel Dovgalyuk wrote:
> > > > This patch fixes exception handling in MIPS.
> > > > MIPS instructions generate severa
> From: Aurelien Jarno [mailto:aurel...@aurel32.net]
> On 2015-06-15 07:53, Pavel Dovgaluk wrote:
> > > From: Aurelien Jarno [mailto:aurel...@aurel32.net]
> > > On 2015-06-10 11:33, Pavel Dovgalyuk wrote:
> > > > This patch fixes exception handling in MIPS.
> > > > MIPS instructions generate severa
On 2015-06-15 07:53, Pavel Dovgaluk wrote:
> > From: Aurelien Jarno [mailto:aurel...@aurel32.net]
> > On 2015-06-10 11:33, Pavel Dovgalyuk wrote:
> > > This patch fixes exception handling in MIPS.
> > > MIPS instructions generate several types of exceptions.
> > > When exception is generated, it br
> From: Aurelien Jarno [mailto:aurel...@aurel32.net]
> On 2015-06-10 11:33, Pavel Dovgalyuk wrote:
> > This patch fixes exception handling in MIPS.
> > MIPS instructions generate several types of exceptions.
> > When exception is generated, it breaks the execution of the current
> > translation
>
On 2015-06-10 11:33, Pavel Dovgalyuk wrote:
> This patch fixes exception handling in MIPS.
> MIPS instructions generate several types of exceptions.
> When exception is generated, it breaks the execution of the current
> translation
> block. Implementation of the exceptions handling in MIPS does n
This patch fixes exception handling in MIPS.
MIPS instructions generate several types of exceptions.
When exception is generated, it breaks the execution of the current translation
block. Implementation of the exceptions handling in MIPS does not correctly
restore icount for the instruction which c
On Fri, 5 Dec 2014, Leon Alrae wrote:
> > I gave it a thought before making this change and concluded it would be
> > the lesser evil (plus loudly manifesting and easily correctable) if
> > someone accidentally makes QEMU refuse to load older images where in
> > fact no compatibility issue exi
On 12/11/2014 18:58, Maciej W. Rozycki wrote:
> On Wed, 12 Nov 2014, Peter Maydell wrote:
>
>>> @@ -208,12 +206,12 @@ int cpu_load(QEMUFile *f, void *opaque,
>>> MIPSCPU *cpu = mips_env_get_cpu(env);
>>> int i;
>>>
>>> -if (version_id < 3) {
>>> +if (version_id != CPU_SAVE_VERSIO
On Mon, 24 Nov 2014, Leon Alrae wrote:
> All the patches up to this one have been applied to mips-next branch
> (available at git://github.com/lalrae/qemu.git), thanks. I'll go through
> the remaining soon.
Thanks. I am now back from a week's vacation and will continue posting
outstanding chan
On 26/11/14 14:01, Paolo Bonzini wrote:
> Use the external qemu-timer API instead.
>
> Signed-off-by: Paolo Bonzini
Acked-by: James Hogan
Thanks
James
> ---
> target-mips/kvm.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target-mips/kvm.c b/target-mips/kvm.c
> i
Use the external qemu-timer API instead.
Signed-off-by: Paolo Bonzini
---
target-mips/kvm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-mips/kvm.c b/target-mips/kvm.c
index 97fd51a..a761ea5 100644
--- a/target-mips/kvm.c
+++ b/target-mips/kvm.c
@@ -439,7 +439,7 @@
On 12/11/2014 15:21, Maciej W. Rozycki wrote:
> Fix microMIPS MOVE16 and MOVEP instructions on 64-bit processors by
> using register addition operations.
>
> This copies the approach taken with MIPS16 MOVE instructions (I8_MOV32R
> and I8_MOVR32 opcodes) and follows the observation that OPC_ADDU
Hi Maciej,
On 10/11/2014 13:46, Maciej W. Rozycki wrote:
> qemu-mips-status.diff
> Index: qemu-git-trunk/target-mips/cpu.h
> ===
> --- qemu-git-trunk.orig/target-mips/cpu.h 2014-11-09 23:44:32.0
> +
> +++ qemu-git-tru
On 10/11/2014 13:45, Maciej W. Rozycki wrote:
> Correct these issues with the handling of CP0.Status for MIPSr6:
>
> * only ignore the bit pattern of 0b11 on writes to CP0.Status.KSU, that
> is for processors that do implement Supervisor Mode, let the bit
> pattern be written to CP0.Status.UM
On 04/11/2014 15:42, Maciej W. Rozycki wrote:
> Enable vectored interrupt support for the 74Kf CPU, reflecting hardware.
>
> Signed-off-by: Maciej W. Rozycki
> ---
> qemu-mips-config-74k-vint.diff
> Index: qemu-git-trunk/target-mips/translate_init.c
> =
On 03/11/2014 18:51, Maciej W. Rozycki wrote:
> CP1.FIR is read-only in hardware so gdbstub must respect it. We already
> respect it for CTC1 instructions, so do it here too.
>
> Signed-off-by: Maciej W. Rozycki
> ---
> Not much to say about it here. Please apply.
>
> Maciej
>
> qemu-mips-
On 03/11/2014 18:47, Maciej W. Rozycki wrote:
> Fix an off-by-one error in `mips_cpu_gdb_write_register' for register
> #72 that is handled further down in that function rather than here,
> matching how `mips_cpu_gdb_read_register' handles it. This register
> slot is a fake anyway, there's noth
On Thu, 13 Nov 2014, Leon Alrae wrote:
> It might be a good idea to split these changes into separate patches to
> have more precise indication about touched subsystem (even though all
> the changes were done in MIPS context). For example "target-mips" and
> "linux-user" rather than just "mips".
On 12/11/2014 18:46, Maciej W. Rozycki wrote:
> On Wed, 12 Nov 2014, Andreas Färber wrote:
>
>> Please consistently use "target-mips: " when that's what you're
>> touching. (For hw/mips/ it's less consistent what to use.)
>
> Sure. What about MIPS changes that span files contained within
> tar
On Wed, 12 Nov 2014, Peter Maydell wrote:
> > @@ -208,12 +206,12 @@ int cpu_load(QEMUFile *f, void *opaque,
> > MIPSCPU *cpu = mips_env_get_cpu(env);
> > int i;
> >
> > -if (version_id < 3) {
> > +if (version_id != CPU_SAVE_VERSION) {
> > return -EINVAL;
> > }
>
>
On Wed, 12 Nov 2014, Andreas Färber wrote:
> Please consistently use "target-mips: " when that's what you're
> touching. (For hw/mips/ it's less consistent what to use.)
Sure. What about MIPS changes that span files contained within
target-mips/ and elsewhere? I have such changes in my queue.
Hi Maciej,
Please consistently use "target-mips: " when that's what you're
touching. (For hw/mips/ it's less consistent what to use.)
Leon, please sanitize subjects before sending them out, it makes them
easier to skim in git-log and cgit.
Thanks,
Andreas
--
SUSE LINUX GmbH, Maxfeldstr. 5, 904
On 12 November 2014 16:07, Maciej W. Rozycki wrote:
> Fix the FP state save/restore operations by saving the `flush_to_zero'
> rather than the `float_detect_tininess' setting. There is no provision
> for the latter in MIPS hardware, whereas the former is controlled by the
> CP1.FCSR.FS bit. As a
Fix the FP state save/restore operations by saving the `flush_to_zero'
rather than the `float_detect_tininess' setting. There is no provision
for the latter in MIPS hardware, whereas the former is controlled by the
CP1.FCSR.FS bit. As a result all the older saved state images are
invalid as t
Fix microMIPS MOVE16 and MOVEP instructions on 64-bit processors by
using register addition operations.
This copies the approach taken with MIPS16 MOVE instructions (I8_MOV32R
and I8_MOVR32 opcodes) and follows the observation that OPC_ADDU expands
to tcg_gen_mov_tl whenever `rt' is 0 and `rs'
Make writes to CP0.Status and CP0.Cause have the same effect as
executing corresponding MTC0 instructions would in Kernel Mode. Also
ignore writes in the user emulation mode.
Currently for requests from the GDB stub we write all the bits across
both registers, ignoring any read-only locations, an
Correct these issues with the handling of CP0.Status for MIPSr6:
* only ignore the bit pattern of 0b11 on writes to CP0.Status.KSU, that
is for processors that do implement Supervisor Mode, let the bit
pattern be written to CP0.Status.UM:R0 freely (of course the value
written to read-only
On Fri, 7 Nov 2014, Leon Alrae wrote:
> >> I was considering making mips32r5-generic less artificial and slowly
> >> evolve it towards some existing MIPS32R5 CPU, for example P5600 (which
> >> supports MSA, but doesn't support DSP ASE). Furthermore, none from the
> >> latest MIPS CPUs supports bot
On 07/11/14 17:36, Maciej W. Rozycki wrote:
> On Fri, 7 Nov 2014, Leon Alrae wrote:
>
>>> I have been working with the current trunk, the change applies
>>> correctly there AFAICT.
>>
>> 55a2201 commit added (1 << CP0C3_MSAP) to CP0_Config3 for
>> mips32r5-generic which is not present on your pa
On Fri, 7 Nov 2014, Leon Alrae wrote:
> > I have been working with the current trunk, the change applies
> > correctly there AFAICT.
>
> 55a2201 commit added (1 << CP0C3_MSAP) to CP0_Config3 for
> mips32r5-generic which is not present on your patch.
Indeed, my mistake for some reason.
> > I
On 07/11/2014 12:33, Maciej W. Rozycki wrote:
> On Fri, 7 Nov 2014, Leon Alrae wrote:
>
>> When I've been applying this patch to my mips-next candidate branch for
>> 2.2 I realized that you haven't rebased it onto the recent version where
>> MSA has been added to mips32r5-generic. Now I don't thin
On Fri, 7 Nov 2014, Leon Alrae wrote:
> When I've been applying this patch to my mips-next candidate branch for
> 2.2 I realized that you haven't rebased it onto the recent version where
> MSA has been added to mips32r5-generic. Now I don't think that having
> DSP and MSA on one CPU makes sense, t
On 05/11/2014 15:26, Leon Alrae wrote:
> On 04/11/2014 15:41, Maciej W. Rozycki wrote:
>> Set the CP0.Config3.DSP2P bit for the 74kf processor and both that bit
>> and the CP0.Config3.DSP bit for the artificial mips32r5-generic and
>> mips64dspr2 processors. They have the DSPr2 ASE enabled in `i
On 05/11/2014 20:16, Maciej W. Rozycki wrote:
> Now as to CP0.Status.CU1, while fixing the 5Kc and 5KEc processors is an
> obvious change, I think the removal of the extra check may not be such.
> The thing is in the original architecture -- and it still stands for CP2
> -- these bits used to
On Wed, 5 Nov 2014, Leon Alrae wrote:
> > qemu-umips-cu1-ex.diff
> > Index: qemu-git-trunk/target-mips/translate.c
> > ===
> > --- qemu-git-trunk.orig/target-mips/translate.c 2014-10-27
> > 04:26:57.0 +
> > +++ qemu-g
Move the call to `update_fcr31' in `helper_float_cvtw_s' after the
exception flag check, for consistency with the remaining helpers that do
it last too.
Signed-off-by: Maciej W. Rozycki
---
I hope there's no question about this, please apply.
Maciej
qemu-mips-op-helper-cvtw_s-fcr31.diff
In
On Wed, 5 Nov 2014, Leon Alrae wrote:
> The actual microMIPS CPU definition is indeed a worthwile addition -
> thanks. It was on my TODO list to upstream such a CPU but I haven't got
> round to it.
You may still be able to contribute here, by adding microMIPS DSP CPUs.
Regrettably I wasn't abl
On 04/11/2014 15:41, Maciej W. Rozycki wrote:
> Set the CP0.Config3.DSP2P bit for the 74kf processor and both that bit
> and the CP0.Config3.DSP bit for the artificial mips32r5-generic and
> mips64dspr2 processors. They have the DSPr2 ASE enabled in `insn_flags'
> and CPUs that implement that A
On 03/11/2014 19:08, Maciej W. Rozycki wrote:
> Make microMIPS FP branches respect CP0.Status.CU1 and trap with a
> Coprocessor Unusable exception if COP1 has been disabled; also trap if
> no FPU is present at all.
>
> Standard MIPS FP instruction encodings have a more regular structure and
> b
On 04/11/2014 15:39, Maciej W. Rozycki wrote:
> Add the M14K and M14Kc processors from MIPS Technologies that are the
> original implementation of the microMIPS ISA. They are dual instruction
> set processors, implementing both the microMIPS and the standard MIPSr32
> ISA.
>
> These processors
On 04/11/2014 15:37, Maciej W. Rozycki wrote:
> Make the data type used for the CP0.Config4 and CP0.Config5 registers
> and their mask signed, for consistency with the remaining 32-bit CP0
> registers, like CP0.Config0, etc.
>
> Signed-off-by: Maciej W. Rozycki
> ---
> qemu-mips-config-int32_t.
On 03/11/2014 18:36, Maciej W. Rozycki wrote:
> Fix the regression introduced with commit
> 47934d0aadc075b05ce2d9e8a44fa6a46edd1afa [hw: move ISA bridges and
> devices to hw/isa/, configure with default-configs/], by removing
> CONFIG_VT82C686 from configurations that previously did not enable
Set the CP0.Config3.DSP2P bit for the 74kf processor and both that bit
and the CP0.Config3.DSP bit for the artificial mips32r5-generic and
mips64dspr2 processors. They have the DSPr2 ASE enabled in `insn_flags'
and CPUs that implement that ASE need to have both CP0.Config3.DSP and
CP0.Config3.
Enable vectored interrupt support for the 74Kf CPU, reflecting hardware.
Signed-off-by: Maciej W. Rozycki
---
qemu-mips-config-74k-vint.diff
Index: qemu-git-trunk/target-mips/translate_init.c
===
--- qemu-git-trunk.orig/target-mips/t
Add the M14K and M14Kc processors from MIPS Technologies that are the
original implementation of the microMIPS ISA. They are dual instruction
set processors, implementing both the microMIPS and the standard MIPSr32
ISA.
These processors correspond to the M4K and 4KEc CPUs respectively,
except
Make the data type used for the CP0.Config4 and CP0.Config5 registers
and their mask signed, for consistency with the remaining 32-bit CP0
registers, like CP0.Config0, etc.
Signed-off-by: Maciej W. Rozycki
---
qemu-mips-config-int32_t.diff
Index: qemu-git-trunk/target-mips/cpu.h
===
Define macros for CP0.Config3 and CP0.Config4 bits. These used to be
exhaustive as at MIPS32r3, but more bits may have been added since.
Signed-off-by: Maciej W. Rozycki
---
More can be added later on. For the time being, please apply.
Maciej
qemu-mips-config.diff
Index: qemu-git-trunk/ta
Add the 5KEc and 5KEf processors from MIPS Technologies that are the
original implementation of the MIPS64r2 ISA.
Silicon for these processors has never been taped out and no soft cores
were released even. They do exist though, a CP0.PRId value has been
assigned and experimental RTLs produced
Make microMIPS FP branches respect CP0.Status.CU1 and trap with a
Coprocessor Unusable exception if COP1 has been disabled; also trap if
no FPU is present at all.
Standard MIPS FP instruction encodings have a more regular structure and
branches are covered with a single umbrella along other ins
CP1.FIR is read-only in hardware so gdbstub must respect it. We already
respect it for CTC1 instructions, so do it here too.
Signed-off-by: Maciej W. Rozycki
---
Not much to say about it here. Please apply.
Maciej
qemu-mips-fir.diff
Index: qemu-git-trunk/target-mips/gdbstub.c
=
Fix an off-by-one error in `mips_cpu_gdb_write_register' for register
#72 that is handled further down in that function rather than here,
matching how `mips_cpu_gdb_read_register' handles it. This register
slot is a fake anyway, there's nothing in hardware that corresponds to
it.
Signed-off-b
Fix the regression introduced with commit
47934d0aadc075b05ce2d9e8a44fa6a46edd1afa [hw: move ISA bridges and
devices to hw/isa/, configure with default-configs/], by removing
CONFIG_VT82C686 from configurations that previously did not enable it.
That southbridge is only available on Fulong pla
MIPS Jazz chipset doesn't seem to raise data bus exceptions on invalid accesses.
However, there is no easy way to prevent them. Creating a big memory region
for the whole address space doesn't prevent memory core to directly call
unassigned_mem_read/write which in turn call cpu->do_unassigned_acces
Hi Andreas,
On 23/08/13 12:08, Andreas Färber wrote:
> Am 23.08.2013 09:59, schrieb Leon Alrae:
>> From: James Hogan
>>
>> Commit a427338 (mips_malta: correct reading MIPS revision at 0x1fc00010)
>> altered the behaviour of the monitor flash mapping at the reset address
>> by making it read only.
Am 23.08.2013 09:59, schrieb Leon Alrae:
> From: James Hogan
>
> Commit a427338 (mips_malta: correct reading MIPS revision at 0x1fc00010)
> altered the behaviour of the monitor flash mapping at the reset address
> by making it read only. However this causes data bus error exceptions
> when it is
From: James Hogan
Commit a427338 (mips_malta: correct reading MIPS revision at 0x1fc00010)
altered the behaviour of the monitor flash mapping at the reset address
by making it read only. However this causes data bus error exceptions
when it is written to since it is effectively unassigned memory
On 01/10/2013 04:12 PM, Peter Maydell wrote:
> This is an OS/ABI specific define, right? I don't think it
> belongs in the target-mips header file. Since it only has one
> user, I think you could reasonably just put it in linux-user/main.c.
The enum will only be used in the MIPS CPU loop. I orig
On 01/10/2013 03:57 PM, Stefan Weil wrote:
> please check your patch before submitting it to qemu-devel.
> See also http://wiki.qemu.org/Contribute/SubmitAPatch.
Ah, thanks for the pointer. I have fixed the style violations.
--
Meador Inge
CodeSourcery / Mentor Embedded
On 10 January 2013 21:46, Meador Inge wrote:
> --- a/target-mips/cpu.h
> +++ b/target-mips/cpu.h
> @@ -620,6 +620,12 @@ enum {
> /* Dummy exception for conditional stores. */
> #define EXCP_SC 0x100
>
> +/* Break codes */
> +enum {
> +BRK_OVERFLOW = 6,
> +BRK_DIVZERO = 7
> +};
This is
Am 10.01.2013 22:46, schrieb Meador Inge:
GCC and GAS are capable of generating traps or breaks to check for
division by zero. Additionally, GAS is capable of generating traps
or breaks to check for overflow on certain division and multiplication
operations. The Linux kernel translates these tr
GCC and GAS are capable of generating traps or breaks to check for
division by zero. Additionally, GAS is capable of generating traps
or breaks to check for overflow on certain division and multiplication
operations. The Linux kernel translates these traps and breaks into
signals. This patch imp
012 6:38 AM
> > To: qemu-devel@nongnu.org
> > Cc: Aurelien Jarno
> > Subject: [Qemu-devel] [PATCH] mips/malta: fix CBUS UART interrupt pin
> >
> > According to the MIPS Malta Developement Platform User's Manual, the
> > i8259 interrupt controller is supposed t
> -Original Message-
> From: qemu-devel-bounces+ericj=mips@nongnu.org [mailto:qemu-devel-
> bounces+ericj=mips@nongnu.org] On Behalf Of Aurelien Jarno
> Sent: Wednesday, November 14, 2012 6:38 AM
> To: qemu-devel@nongnu.org
> Cc: Aurelien Jarno
> Subject: [Qem
According to the MIPS Malta Developement Platform User's Manual, the
i8259 interrupt controller is supposed to be connected to the hardware
IRQ0, and the CBUS UART to the hardware interrupt 2.
In QEMU they are both connected to hardware interrupt 0, the CBUS UART
interrupt being wrong. This patch
On Fri, Jun 08, 2012 at 02:04:40AM +0100, Maciej W. Rozycki wrote:
>
> This change updates the CPU reset sequence to use a common piece of code
> that figures out CPU state flags, fixing the problem with MIPS_HFLAG_COP1X
> not being set where applicable that causes floating-point MADD family
>
On Mon, Aug 27, 2012 at 09:53:29AM +0100, Richard Sandiford wrote:
> The FS input to CVT.PS.S is the high half and FT is the low half.
> tcg_gen_concat_i32_i64 takes the low half first, so the operands
> were in the wrong order.
>
> Signed-off-by: Richard Sandiford
> ---
> target-mips/translate.
On Mon, Aug 27, 2012 at 09:50:38AM +0100, Richard Sandiford wrote:
> Read the second input operand of RECIP2.S and RECIP2.PS from FT rather
> than FD. RECIP2.D is already correct.
>
> Signed-off-by: Richard Sandiford
> ---
> target-mips/translate.c |4 ++--
> 1 files changed, 2 insertions(+
On Mon, Aug 27, 2012 at 9:50 AM, Richard Sandiford
wrote:
> Read the second input operand of RECIP2.S and RECIP2.PS from FT rather
> than FD. RECIP2.D is already correct.
>
> Signed-off-by: Richard Sandiford
> ---
> target-mips/translate.c |4 ++--
> 1 files changed, 2 insertions(+), 2 dele
On Mon, Aug 27, 2012 at 9:53 AM, Richard Sandiford
wrote:
> The FS input to CVT.PS.S is the high half and FT is the low half.
> tcg_gen_concat_i32_i64 takes the low half first, so the operands
> were in the wrong order.
>
> Signed-off-by: Richard Sandiford
> ---
> target-mips/translate.c |2
The FS input to CVT.PS.S is the high half and FT is the low half.
tcg_gen_concat_i32_i64 takes the low half first, so the operands
were in the wrong order.
Signed-off-by: Richard Sandiford
---
target-mips/translate.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/targe
Read the second input operand of RECIP2.S and RECIP2.PS from FT rather
than FD. RECIP2.D is already correct.
Signed-off-by: Richard Sandiford
---
target-mips/translate.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
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