[Qemu-devel] [PATCH][MIPS] add "lwu" instruction

[Marius Groeger]

Hello All,

this patch adds support for the LWU instruction on MIPS.

Regards,
Marius

--
Marius Groeger <[EMAIL PROTECTED]>
SYSGO AG                      Embedded and Real-Time Software
Voice: +49 6136 9948 0                  FAX: +49 6136 9948 10
www.sysgo.com | www.elinos.com | www.osek.de | www.pikeos.com
--- qemu-0.8.0/target-mips/op_mem.c     5 Dec 2005 19:59:36 -0000       1.2
+++ qemu-0.8.0/target-mips/op_mem.c     12 Apr 2006 20:17:24 -0000
@@ -61,6 +61,12 @@
     RETURN();
 }
 
+void glue(op_lwu, MEMSUFFIX) (void)
+{
+    T0 = glue(ldl, MEMSUFFIX)(T0);
+    RETURN();
+}
+
 void glue(op_sw, MEMSUFFIX) (void)
 {
     glue(stl, MEMSUFFIX)(T0, T1);
Index: target-mips/translate.c
===================================================================
RCS file: /sources/qemu/qemu/target-mips/translate.c,v
retrieving revision 1.11
diff -u -r1.11 translate.c
--- qemu-0.8.0/target-mips/translate.c  5 Dec 2005 19:59:36 -0000       1.11
+++ qemu-0.8.0/target-mips/translate.c  12 Apr 2006 20:17:24 -0000
@@ -96,6 +96,7 @@
     OPC_LBU      = 0x24,
     OPC_LHU      = 0x25,
     OPC_LWR      = 0x26,
+    OPC_LWU      = 0x27,
     OPC_SB       = 0x28,
     OPC_SH       = 0x29,
     OPC_SWL      = 0x2A,
@@ -384,6 +385,7 @@
 OP_ST_TABLE(dr);
 #endif
 OP_LD_TABLE(w);
+OP_LD_TABLE(wu);
 OP_LD_TABLE(wl);
 OP_LD_TABLE(wr);
 OP_ST_TABLE(w);
@@ -463,6 +465,11 @@
         GEN_STORE_TN_REG(rt, T0);
         opn = "lw";
         break;
+    case OPC_LWU:
+        op_ldst(lwu);
+        GEN_STORE_TN_REG(rt, T0);
+        opn = "lwu";
+        break;
     case OPC_SW:
 #if defined (MIPS_HAS_UNALIGNED_LS)
     case OPC_USW:
@@ -1180,7 +1187,7 @@
     const unsigned char *opn = "unk";
 
     if (!(ctx->CP0_Status & (1 << CP0St_CU0)) &&
-        !(ctx->hflags & MIPS_HFLAG_UM) &&
+        (ctx->hflags & MIPS_HFLAG_UM) &&
         !(ctx->hflags & MIPS_HFLAG_ERL) &&
         !(ctx->hflags & MIPS_HFLAG_EXL)) {
         if (loglevel & CPU_LOG_TB_IN_ASM) {
@@ -1189,6 +1196,7 @@
         generate_exception_err (ctx, EXCP_CpU, 0);
         return;
     }
+
     switch (opc) {
     case OPC_MFC0:
         if (rt == 0) {
@@ -1320,6 +1328,12 @@
     uint16_t op, op1;
     int16_t imm;
 
+       /* make sure instructions are on a word boundary */
+       if (ctx->pc & 0x3) {
+               generate_exception(ctx, EXCP_AdEL);
+               return;
+       }
+
     if ((ctx->hflags & MIPS_HFLAG_BMASK) == MIPS_HFLAG_BL) {
         /* Handle blikely not taken case */
         MIPS_DEBUG("blikely condition (%08x)", ctx->pc + 4);
@@ -1475,8 +1489,7 @@
     case 0x14 ... 0x17:
         gen_compute_branch(ctx, op, rs, rt, imm << 2);
         return;
-    case 0x20 ... 0x26: /* Load and stores */
-    case 0x28 ... 0x2E:
+    case 0x20 ... 0x2E: /* Load and stores */
     case 0x30:
     case 0x38:
         gen_ldst(ctx, op, rt, rs, imm);

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