The shift instructions on the SPARC target currently take into account
the whole register as the shift count. According to the SPARC v8 and v9
manuals, only the lower 5 bits should be taken into account for 32-bit
instructions (SLL, SRL, SRA), and only the lower 6 bits for 64-bit
instructions (SLL
On Sun, Apr 01, 2007 at 11:32:06AM +0200, Blue Swirl wrote:
> >The shift instructions on the SPARC target currently take into account
> >the whole register as the shift count. According to the SPARC v8 and v9
> >manuals, only the lower 5 bits should be taken into account for 32-bit
> >instructions
