Greetings,
as part of the debugging for the previous problem on FreeBSD and based on the
documentation from Intel from :
http://www.intel.com/design/intarch/datashts/290550.htm
the following patch does some cleanup in the current sources so that a reset
for function 1 (the IDE interface) for PIIX and PIIX3 is supported and PIIX
could be used instead of PIIX3 if needed (by swapping the corresponding
piix?_init and pci_piix?_ide_init functions in hw/pc.c or creating another
cloned emulated "pc").
most of the code is currently not linked, except for the addition of
piix3_reset to the reset for function 1 of PIIX3 to match the spec and the
removal of 2 duplicated lines on the reset functions for PIIX3 and PIIX4, but
it is left behind as it could be useful for a new target for testing of legacy
OSs or embedded.
Carlo
Index: hw/ide.c
===================================================================
RCS file: /sources/qemu/qemu/hw/ide.c,v
retrieving revision 1.51
diff -u -r1.51 ide.c
--- hw/ide.c 20 Jan 2007 01:12:17 -0000 1.51
+++ hw/ide.c 22 Jan 2007 09:50:20 -0000
@@ -2577,6 +2579,55 @@
return 0;
}
+static void piix3_reset(PCIIDEState *d)
+{
+ uint8_t *pci_conf = d->dev.config;
+
+ pci_conf[0x04] = 0x00;
+ pci_conf[0x05] = 0x00;
+ pci_conf[0x06] = 0x80; /* FBC */
+ pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
+ pci_conf[0x20] = 0x01; /* BMIBA: 20-23h */
+}
+
+void pci_piix_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn)
+{
+ PCIIDEState *d;
+ uint8_t *pci_conf;
+
+ /* register a function 1 of PIIX */
+ d = (PCIIDEState *)pci_register_device(bus, "PIIX IDE",
+ sizeof(PCIIDEState),
+ devfn,
+ NULL, NULL);
+ d->type = IDE_TYPE_PIIX3;
+
+ pci_conf = d->dev.config;
+ pci_conf[0x00] = 0x86; // Intel
+ pci_conf[0x01] = 0x80;
+ pci_conf[0x02] = 0x30;
+ pci_conf[0x03] = 0x12;
+ pci_conf[0x08] = 0x02; // Step A1
+ pci_conf[0x09] = 0x80; // legacy ATA mode
+ pci_conf[0x0a] = 0x01; // class_sub = PCI_IDE
+ pci_conf[0x0b] = 0x01; // class_base = PCI_mass_storage
+ pci_conf[0x0e] = 0x00; // header_type
+
+ piix3_reset(d);
+
+ pci_register_io_region((PCIDevice *)d, 4, 0x10,
+ PCI_ADDRESS_SPACE_IO, bmdma_map);
+
+ ide_init2(&d->ide_if[0], hd_table[0], hd_table[1],
+ pic_set_irq_new, isa_pic, 14);
+ ide_init2(&d->ide_if[2], hd_table[2], hd_table[3],
+ pic_set_irq_new, isa_pic, 15);
+ ide_init_ioport(&d->ide_if[0], 0x1f0, 0x3f6);
+ ide_init_ioport(&d->ide_if[2], 0x170, 0x376);
+
+ register_savevm("ide", 0, 1, pci_ide_save, pci_ide_load, d);
+}
+
/* hd_table must contain 4 block drivers */
/* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */
void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn)
@@ -2601,6 +2652,8 @@
pci_conf[0x0b] = 0x01; // class_base = PCI_mass_storage
pci_conf[0x0e] = 0x00; // header_type
+ piix3_reset(d);
+
pci_register_io_region((PCIDevice *)d, 4, 0x10,
PCI_ADDRESS_SPACE_IO, bmdma_map);
Index: hw/piix_pci.c
===================================================================
RCS file: /sources/qemu/qemu/hw/piix_pci.c,v
retrieving revision 1.8
diff -u -r1.8 piix_pci.c
--- hw/piix_pci.c 15 Jan 2007 17:08:08 -0000 1.8
+++ hw/piix_pci.c 22 Jan 2007 09:50:20 -0000
@@ -246,7 +246,6 @@
pci_conf[0x80] = 0x00;
pci_conf[0x82] = 0x00;
pci_conf[0xa0] = 0x08;
- pci_conf[0xa0] = 0x08;
pci_conf[0xa2] = 0x00;
pci_conf[0xa3] = 0x00;
pci_conf[0xa4] = 0x00;
@@ -284,7 +283,6 @@
pci_conf[0x80] = 0x00;
pci_conf[0x82] = 0x00;
pci_conf[0xa0] = 0x08;
- pci_conf[0xa0] = 0x08;
pci_conf[0xa2] = 0x00;
pci_conf[0xa3] = 0x00;
pci_conf[0xa4] = 0x00;
@@ -312,6 +310,31 @@
return pci_device_load(d, f);
}
+int piix_init(PCIBus *bus, int devfn)
+{
+ PCIDevice *d;
+ uint8_t *pci_conf;
+
+ d = pci_register_device(bus, "PIIX", sizeof(PCIDevice),
+ devfn, NULL, NULL);
+ register_savevm("PIIX", 0, 2, piix_save, piix_load, d);
+
+ piix3_dev = d;
+ pci_conf = d->config;
+
+ pci_conf[0x00] = 0x86; // Intel
+ pci_conf[0x01] = 0x80;
+ pci_conf[0x02] = 0x2E; // 82371FB PIIX PCI-to-ISA bridge
+ pci_conf[0x03] = 0x12;
+ pci_conf[0x08] = 0x02; // Step A1
+ pci_conf[0x0a] = 0x01; // class_sub = PCI_ISA
+ pci_conf[0x0b] = 0x06; // class_base = PCI_bridge
+ pci_conf[0x0e] = 0x80; // header_type = PCI_multifunction, generic
+
+ piix3_reset(d);
+ return d->devfn;
+}
+
int piix3_init(PCIBus *bus, int devfn)
{
PCIDevice *d;
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