Hello All,
this avoids flushing of global TLB entries for differing ASIDs.
Thiemo
Index: qemu-work/target-mips/op_helper.c
===================================================================
--- qemu-work.orig/target-mips/op_helper.c 2006-02-19 01:30:55.000000000
+0000
+++ qemu-work/target-mips/op_helper.c 2006-02-19 16:18:43.000000000 +0000
@@ -622,13 +622,14 @@
void do_tlbr (void)
{
tlb_t *tlb;
+ uint8_t ASID;
int size;
+ ASID = env->CP0_EntryHi & 0xFF;
tlb = &env->tlb[env->CP0_index & (MIPS_TLB_NB - 1)];
/* If this will change the current ASID, flush qemu's TLB. */
- /* FIXME: Could avoid flushing things which match global entries... */
- if ((env->CP0_EntryHi & 0xFF) != tlb->ASID)
+ if (ASID != tlb->ASID && tlb->G != 1)
tlb_flush (env, 1);
env->CP0_EntryHi = tlb->VPN | tlb->ASID;
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