Re: [Qemu-devel] [PATCH] SPARC64: fix VIS1 SIMD signed compare instructions

2011-07-20 Thread Blue Swirl
Thanks, applied. On Mon, Jul 18, 2011 at 9:00 AM, Tsuneo Saito wrote: > The destination registers of SIMD signed compare instructions > (fcmp*<16|32>) are not FP registers but general purpose r registers. > Comparisons should be freg_rs1 CMP freg_rs2, that were reversed. > > Signed-off-by: Tsuneo

[Qemu-devel] [PATCH] SPARC64: fix VIS1 SIMD signed compare instructions

2011-07-17 Thread Tsuneo Saito
The destination registers of SIMD signed compare instructions (fcmp*<16|32>) are not FP registers but general purpose r registers. Comparisons should be freg_rs1 CMP freg_rs2, that were reversed. Signed-off-by: Tsuneo Saito --- target-sparc/helper.h|4 ++-- target-sparc/op_helper.c | 2