On Tue, 26 Mar 2019 10:49:11 PDT (-0700), chout...@adacore.com wrote:
Hi Palmer,
On 26/03/2019 09:58, Palmer Dabbelt wrote:
Do you have anything that actually glues this to a machine so I can test it?
In this patch I do instantiate the device in sifive_e machine.
OK, that's what I thought
Hi Palmer,
On 26/03/2019 09:58, Palmer Dabbelt wrote:
> Do you have anything that actually glues this to a machine so I can test it?
>
In this patch I do instantiate the device in sifive_e machine.
Regards,
On Tue, 12 Feb 2019 09:38:39 PST (-0800), chout...@adacore.com wrote:
QEMU model of the GPIO device on the SiFive E300 series SOCs.
The pins are not used by a board definition yet, however this
implementation can already be used to trigger GPIO interrupts from the
software by configuring a pin
On Wed, Feb 13, 2019 at 1:36 PM Peter Maydell wrote:
>
> On Wed, 13 Feb 2019 at 18:54, Thomas Huth wrote:
> >
> > On 2019-02-13 18:14, Peter Maydell wrote:
> > > On Wed, 13 Feb 2019 at 00:13, Alistair Francis
> > > wrote:
> > >> I know the other RISC-V files don't do it, but this should go in
On Wed, 13 Feb 2019 at 18:54, Thomas Huth wrote:
>
> On 2019-02-13 18:14, Peter Maydell wrote:
> > On Wed, 13 Feb 2019 at 00:13, Alistair Francis wrote:
> >> I know the other RISC-V files don't do it, but this should go in the
> >> hw/gpio directory instead of hw/riscv.
> >
> > It might be nice
On Wed, 13 Feb 2019 10:54:08 PST (-0800), th...@redhat.com wrote:
On 2019-02-13 18:14, Peter Maydell wrote:
On Wed, 13 Feb 2019 at 00:13, Alistair Francis wrote:
I know the other RISC-V files don't do it, but this should go in the
hw/gpio directory instead of hw/riscv.
It might be nice to
On 2019-02-13 18:14, Peter Maydell wrote:
> On Wed, 13 Feb 2019 at 00:13, Alistair Francis wrote:
>> I know the other RISC-V files don't do it, but this should go in the
>> hw/gpio directory instead of hw/riscv.
>
> It might be nice to move those existing riscv devices into
> their proper places
On Wed, 13 Feb 2019 at 00:13, Alistair Francis wrote:
> I know the other RISC-V files don't do it, but this should go in the
> hw/gpio directory instead of hw/riscv.
It might be nice to move those existing riscv devices into
their proper places at some point: should be a fairly easy
cleanup
On Tue, Feb 12, 2019 at 9:39 AM Fabien Chouteau wrote:
>
> QEMU model of the GPIO device on the SiFive E300 series SOCs.
>
> The pins are not used by a board definition yet, however this
> implementation can already be used to trigger GPIO interrupts from the
> software by configuring a pin as
QEMU model of the GPIO device on the SiFive E300 series SOCs.
The pins are not used by a board definition yet, however this
implementation can already be used to trigger GPIO interrupts from the
software by configuring a pin as both output and input.
Signed-off-by: Fabien Chouteau
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