On 17.07.2018 16:49, Peter Maydell wrote:
On 17 July 2018 at 14:42, Julia Suvorova wrote:
On 17.07.2018 16:09, Peter Maydell wrote:
This should be outside the "if v8" if(), because you also want it for v6M
(giving you the v6M CCR value of STKALIGN and UNALIGN_TRP set and all
other bits
On 17 July 2018 at 14:42, Julia Suvorova wrote:
> On 17.07.2018 16:09, Peter Maydell wrote:
>> This should be outside the "if v8" if(), because you also want it for v6M
>> (giving you the v6M CCR value of STKALIGN and UNALIGN_TRP set and all
>> other bits clear).
>
>
> This is the main problem.
On 17.07.2018 16:09, Peter Maydell wrote:
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index a914ce4e8c..3788cb773d 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -220,6 +220,11 @@ static void arm_cpu_reset(CPUState *s)
env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK;
On 13 July 2018 at 11:30, Julia Suvorova wrote:
> Forbid stack alignment change. (CCR)
> Reserve FAULTMASK, BASEPRI registers.
> Report any fault as HardFault. Disable MemManage, BusFault and
> UsageFault, so they always escalated to HardFault. (SHCSR)
>
> Signed-off-by: Julia Suvorova
> ---
>
On Fri, Jul 13, 2018 at 01:30:59PM +0300, Julia Suvorova wrote:
> Forbid stack alignment change. (CCR)
> Reserve FAULTMASK, BASEPRI registers.
> Report any fault as HardFault. Disable MemManage, BusFault and
> UsageFault, so they always escalated to HardFault. (SHCSR)
>
> Signed-off-by: Julia
Forbid stack alignment change. (CCR)
Reserve FAULTMASK, BASEPRI registers.
Report any fault as HardFault. Disable MemManage, BusFault and
UsageFault, so they always escalated to HardFault. (SHCSR)
Signed-off-by: Julia Suvorova
---
This is the last cortex-m0 patch.
hw/intc/armv7m_nvic.c | 10
