On Mon, May 22, 2017 at 5:46 AM, Jason Wang wrote:
>
>
> On 2017年05月19日 22:04, Sameeh Jubran wrote:
>
>> On Fri, May 19, 2017 at 9:25 AM, Jason Wang wrote:
>>
>>
>>> On 2017年05月17日 19:46, Sameeh Jubran wrote:
>>>
>>> The bug was caused by the "receive overrun" (bit #6 of the ICR register)
i
On 2017年05月19日 22:04, Sameeh Jubran wrote:
On Fri, May 19, 2017 at 9:25 AM, Jason Wang wrote:
On 2017年05月17日 19:46, Sameeh Jubran wrote:
The bug was caused by the "receive overrun" (bit #6 of the ICR register)
interrupt
which would be triggered post migration in a heavy traffic environmen
On Fri, May 19, 2017 at 9:25 AM, Jason Wang wrote:
>
>
> On 2017年05月17日 19:46, Sameeh Jubran wrote:
>
>> The bug was caused by the "receive overrun" (bit #6 of the ICR register)
>> interrupt
>> which would be triggered post migration in a heavy traffic environment.
>> Even though the
>> "receive
On 2017年05月17日 19:46, Sameeh Jubran wrote:
The bug was caused by the "receive overrun" (bit #6 of the ICR register)
interrupt
which would be triggered post migration in a heavy traffic environment. Even
though the
"receive overrun" bit (#6) is masked out by the IMS register (refer to the log
On 18/05/2017 12:04, Dr. David Alan Gilbert wrote:
> * Sameeh Jubran (sam...@daynix.com) wrote:
>> The bug was caused by the "receive overrun" (bit #6 of the ICR register)
>> interrupt
>> which would be triggered post migration in a heavy traffic environment. Even
>> though the
>> "receive over
* Sameeh Jubran (sam...@daynix.com) wrote:
> The bug was caused by the "receive overrun" (bit #6 of the ICR register)
> interrupt
> which would be triggered post migration in a heavy traffic environment. Even
> though the
> "receive overrun" bit (#6) is masked out by the IMS register (refer to th
> On 17 May 2017, at 14:46 PM, Sameeh Jubran wrote:
>
> The bug was caused by the "receive overrun" (bit #6 of the ICR register)
> interrupt
> which would be triggered post migration in a heavy traffic environment. Even
> though the
> "receive overrun" bit (#6) is masked out by the IMS registe
The bug was caused by the "receive overrun" (bit #6 of the ICR register)
interrupt
which would be triggered post migration in a heavy traffic environment. Even
though the
"receive overrun" bit (#6) is masked out by the IMS register (refer to the log
below)
the driver still receives an interrupt