Re: [Qemu-devel] [PATCH] mips: Set the CP0.Config3.DSP and CP0.Config3.DSP2P bits

2014-11-07 Thread Maciej W. Rozycki
On Fri, 7 Nov 2014, Leon Alrae wrote: > >> I was considering making mips32r5-generic less artificial and slowly > >> evolve it towards some existing MIPS32R5 CPU, for example P5600 (which > >> supports MSA, but doesn't support DSP ASE). Furthermore, none from the > >> latest MIPS CPUs supports bot

Re: [Qemu-devel] [PATCH] mips: Set the CP0.Config3.DSP and CP0.Config3.DSP2P bits

2014-11-07 Thread Leon Alrae
On 07/11/14 17:36, Maciej W. Rozycki wrote: > On Fri, 7 Nov 2014, Leon Alrae wrote: > >>> I have been working with the current trunk, the change applies >>> correctly there AFAICT. >> >> 55a2201 commit added (1 << CP0C3_MSAP) to CP0_Config3 for >> mips32r5-generic which is not present on your pa

Re: [Qemu-devel] [PATCH] mips: Set the CP0.Config3.DSP and CP0.Config3.DSP2P bits

2014-11-07 Thread Maciej W. Rozycki
On Fri, 7 Nov 2014, Leon Alrae wrote: > > I have been working with the current trunk, the change applies > > correctly there AFAICT. > > 55a2201 commit added (1 << CP0C3_MSAP) to CP0_Config3 for > mips32r5-generic which is not present on your patch. Indeed, my mistake for some reason. > > I

Re: [Qemu-devel] [PATCH] mips: Set the CP0.Config3.DSP and CP0.Config3.DSP2P bits

2014-11-07 Thread Leon Alrae
On 07/11/2014 12:33, Maciej W. Rozycki wrote: > On Fri, 7 Nov 2014, Leon Alrae wrote: > >> When I've been applying this patch to my mips-next candidate branch for >> 2.2 I realized that you haven't rebased it onto the recent version where >> MSA has been added to mips32r5-generic. Now I don't thin

Re: [Qemu-devel] [PATCH] mips: Set the CP0.Config3.DSP and CP0.Config3.DSP2P bits

2014-11-07 Thread Maciej W. Rozycki
On Fri, 7 Nov 2014, Leon Alrae wrote: > When I've been applying this patch to my mips-next candidate branch for > 2.2 I realized that you haven't rebased it onto the recent version where > MSA has been added to mips32r5-generic. Now I don't think that having > DSP and MSA on one CPU makes sense, t

Re: [Qemu-devel] [PATCH] mips: Set the CP0.Config3.DSP and CP0.Config3.DSP2P bits

2014-11-07 Thread Leon Alrae
On 05/11/2014 15:26, Leon Alrae wrote: > On 04/11/2014 15:41, Maciej W. Rozycki wrote: >> Set the CP0.Config3.DSP2P bit for the 74kf processor and both that bit >> and the CP0.Config3.DSP bit for the artificial mips32r5-generic and >> mips64dspr2 processors. They have the DSPr2 ASE enabled in `i

Re: [Qemu-devel] [PATCH] mips: Set the CP0.Config3.DSP and CP0.Config3.DSP2P bits

2014-11-05 Thread Leon Alrae
On 04/11/2014 15:41, Maciej W. Rozycki wrote: > Set the CP0.Config3.DSP2P bit for the 74kf processor and both that bit > and the CP0.Config3.DSP bit for the artificial mips32r5-generic and > mips64dspr2 processors. They have the DSPr2 ASE enabled in `insn_flags' > and CPUs that implement that A

[Qemu-devel] [PATCH] mips: Set the CP0.Config3.DSP and CP0.Config3.DSP2P bits

2014-11-04 Thread Maciej W. Rozycki
Set the CP0.Config3.DSP2P bit for the 74kf processor and both that bit and the CP0.Config3.DSP bit for the artificial mips32r5-generic and mips64dspr2 processors. They have the DSPr2 ASE enabled in `insn_flags' and CPUs that implement that ASE need to have both CP0.Config3.DSP and CP0.Config3.