On 8/13/19 4:31 PM, Paul A. Clarke wrote:
> +TCGv_i64 mask = tcg_const_i64(FP_MODE | FP_STATUS | FP_ENABLES);
> +tcg_gen_and_i64(t0, t0, mask);
Better as
tcg_gen_andi_i64(t0, t0, FP_MODE | FP_STATUS | FP_ENABLES);
You failed to free the temporary that you allocated here.
r~
Patchew URL:
https://patchew.org/QEMU/1565710319-1026-1-git-send-email...@us.ibm.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH] ppc: Add support for 'mffsl' instruction
Message-id: 1565710319-1026-1-git-send
From: "Paul A. Clarke"
ISA 3.0B added a set of Floating-Point Status and Control Register (FPSCR)
instructions: mffsce, mffscdrn, mffscdrni, mffscrn, mffscrni, mffsl.
This patch adds support for 'mffsl'.
'mffsl' is identical to 'mffs', except it only returns mode, status, and enable
bits from
